MPC8536DS Freescale, MPC8536DS Datasheet - Page 115

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MPC8536DS

Manufacturer Part Number
MPC8536DS
Description
Manufacturer
Freescale
Datasheet

Specifications of MPC8536DS

Lead Free Status / RoHS Status
Compliant
3.2
3.2.1
Each of the PLLs listed above is provided with power through independent power supply pins (AV
AV
preferably these voltages will be derived directly from V
There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to provide independent
filter circuits per PLL power supply as illustrated in
to each PLL the opportunity to cause noise injection from one PLL to the other is reduced.
This circuit is intended to filter noise in the PLLs resonant frequency range from a 500 kHz to 10 MHz range. It should be built
with surface mount capacitors with minimum Effective Series Inductance (ESL). Consistent with the recommendations of Dr.
Howard Johnson in High Speed Digital Design: A Handbook of Black Magic (Prentice Hall, 1993), multiple small capacitors
of equal value are recommended over a single large value capacitor.
Each circuit should be placed as close as possible to the specific AV
nearby circuits. It should be possible to route directly from the capacitors to the AV
FC-PBGA the footprint, without the inductance of vias.
Figure 75
The AV
the power supplied to the PLL is filtered using a circuit similar to the one shown in following
effectiveness, the filter circuit is placed as closely as possible to the AV
as possible. The ground connection should be near the AV
followed by the 1-µF capacitor, and finally the 1 ohm resistor to the board supply plane. The capacitors are connected from
AV
should be kept short, wide and direct.
Note the following:
Freescale Semiconductor
DD
DD
_PCI, AV
_SRDS n to the ground plane. Use ceramic chip capacitors with the highest possible self-resonant frequency. All traces
DD
AV
Signals on the SerDes interface are fed from the XV
shows the PLL power supply filter Circuit.
_SRDS n signals provides power for the analog portions of the SerDes PLL. To ensure stability of the internal clock,
Power Supply Design and Sequencing
DD
PLL Power Supply Filtering
should be a filtered version of SV
DD
_LBIU, and AV
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
SnV
V
DD
DD
1. An 0805 sized capacitor is recommended for system initial bring-up
Figure 75. MPC8536E PLL Power Supply Filter Circuit
Figure 76. SerDes PLL Power Supply Filter Circuit
DD
_SRDS respectively). The AV
10 Ω
1.0 Ω
2.2 µF
DD
2.2 µF
Figure
.
DD
DD
1
GND
75, one to each of the AV
through a low frequency filter scheme such as the following.
_SRDS n balls. The 0.003-µF capacitor is closest to the balls,
DD
GND
power plane.
Low ESL Surface Mount Capacitors
DD
2.2 µF
DD
2.2 µF
level should always be equivalent to V
DD
pin being supplied to minimize noise coupled from
_SRDS n balls to ensure it filters out as much noise
1
AV
0.003 µF
DD
DD
DD
Power Supply Design and Sequencing
pin, which is on the periphery of 783
pins. By providing independent filters
AV
Figure
DD -
DD
SRDS
76. For maximum
_PLAT, AV
DD
, and
DD
_CORE,
115