MPC8536DS Freescale, MPC8536DS Datasheet - Page 21

• Manufacturer Part Number: MPC8536DS
• Manufacturer: Freescale

Specifications of MPC8536DS

• Lead Free Status / RoHS Status: Compliant

2
2.1
This section covers the ratings, conditions, and other characteristics.
2.1.1
Table 2
Freescale Semiconductor
Core supply voltage
Platform supply voltage
PLL core supply voltage
PLL other supply voltage
Core power supply for SerDes transceivers
Pad power supply for SerDes transceivers and PCI Express
25. When a PCI block is disabled, either the POR config pin that selects between internal and external arbiter must be pulled
26. MDIC[0] is grounded through an 18.2-Ω (full-strength mode) or 36.4-Ω (half-strength mode) precision 1% resistor and
27. Connect to GND through a pull down 1 kΩ resistor
28. It must be the same as VDD_CORE
29. The output pads are tristated and the receivers of pad inputs are disabled during the Deep Sleep state when
30. DDRCLK input is only required when the DDR controller is running in asynchronous mode. When the DDR controller is
31. EC_GTX_CLK125 is a 125-MHz input clock shared among all eTSEC ports in the following modes: GMII, TBI, RGMII and
32. SDHC_WP is active low signal, which follows SDHC Host controller specification. However, it is reversed polarity for
down to select external arbiter if there is any other PCI device connected on the PCI bus, or leave the address pins as “No
Connect” or terminated through 2–10 KΩ pull-up resistors with the default of internal arbiter if the address pins are not
connected to any other PCI device. The PCI block will drive the address pins if it is configured to be the PCI arbiter—through
POR config pins—irrespective of whether it is disabled via the DEVDISR register or not. It may cause contention if there is
any other PCI device connected on the bus.
MDIC[1] is connected to GVDD through an 18.2-Ω (full-strength mode) or 36.4-Ω (half-strength mode) precision 1% resistor.
These pins are used for automatic calibration of the DDR IOs.
GCR[DEEPSLEEP_Z] =1.
RTBI. If none of the eTSEC ports is operating in these modes, the EC_GTX_CLK125 input can be tied off to GND.
SD/MMC card specification.
configured to run in synchronous mode via POR setting cfg_ddr_pll[0:2]=111, the DDRCLK input is not required. It is
recommended to tie it off to GND when DDR controller is running in synchronous mode. See the MPC8536E
PowerQUICC™ III Integrated Host Processor Family Reference Manual , Rev.0, Table 4-3 in section 4.2.2 “Clock Signals”,
section 4.4.3.2 “DDR PLL Ratio” and Table 4-10 “DDR Complex Clock PLL Ratio” for more detailed description regarding
DDR controller operation in asynchronous and synchronous modes.
provides the absolute maximum ratings.
Electrical Characteristics
Overall DC Electrical Characteristics
Signal
Absolute Maximum Ratings
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
Characteristic
Table 1. MPC8536E Pinout Listing (continued)
Signal Name
Table 2. Absolute Maximum Ratings
Package Pin Number
SV
XV
AV
V
V
Symbol
DD
DD_CORE
DD,
DD_PLAT
DD_CORE
AV
, S2V
X2V
DD
DD
DD
1
Overall DC Electrical Characteristics
Pin Type
–0.3 to 1.21
–0.3 to 1.21
Max Value
–0.3 to 1.1
–0.3 to 1.1
–0.3 to 1.1
–0.3 to 1.1
Supply
Power
Unit Notes
V
V
V
V
V
V
Notes
—
—
—
—
—
—
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