MPC8536DS Freescale, MPC8536DS Datasheet - Page 77

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MPC8536DS

Manufacturer Part Number
MPC8536DS
Description
Manufacturer
Freescale
Datasheet

Specifications of MPC8536DS

Lead Free Status / RoHS Status
Compliant
Figure 43
Figure 44
2.14
In IRQ edge trigger mode, when an external interrupt signal is asserted (according to the programmed polarity), it must remain
the assertion for at least 3 system clocks (SYSCLK periods).
2.15
This section describes the DC and AC electrical specifications for the IEEE 1149.1 (JTAG) interface of the MPC8536E.
2.15.1
Table 57
Freescale Semiconductor
provides the DC electrical characteristics for the JTAG interface.
provides the eSDHC clock input timing diagram.
provides the data and command input/output timing diagram.
Figure 44. eSDHC Data and Command Input/Output Timing Diagram Referenced to Clock
High-level input voltage
Low-level input voltage
Programmable Interrupt Controller (PIC)
JTAG
External Clock
operational mode
JTAG DC Electrical Characteristics
SD_DAT/CMD
SD_DAT/CMD
External Clock
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
SD_CK
Outputs
eSDHC
Parameter
Inputs
VM
Figure 43. eSDHC Clock Input Timing Diagram
Table 57. JTAG DC Electrical Characteristics
VM
VM = Midpoint Voltage (OV
VM = Midpoint Voltage (OV
t
SHSCK
Symbol
t
VM
V
SHSKHOV
V
IH
IL
t
VM
SHSIVKH
1
VM
VM
Min
-0.3
2
DD
DD
/2)
/2)
t
SHSIXKH
t
SHSCKL
Programmable Interrupt Controller (PIC)
t
SHSCKR
OV
VM
DD
Max
0.8
t
SHSCKH
+ 0.3
t
SHSCKF
Unit
V
V
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