MPC8536DS Freescale, MPC8536DS Datasheet - Page 50
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MPC8536DS
Manufacturer Part Number
MPC8536DS
Description
Manufacturer
Freescale
Datasheet
1.MPC8536DS.pdf
(128 pages)
Specifications of MPC8536DS
Lead Free Status / RoHS Status
Compliant
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Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management
Figure 23
2.9.2.5
When the eTSEC is configured for TBI modes, all clocks are supplied from external sources to the relevant eTSEC interface.
In single-clock TBI mode, when a 125-MHz TBI receive clock is supplied on TSECn pin (no receive clock is used on in this
mode, whereas for the dual-clock mode this is the PMA0 receive clock). The 125-MHz transmit clock is applied on the in all
TBI modes.
A summary of the single-clock TBI mode AC specifications for receive appears in
50
At recommended operating conditions with LV
RX_CLK clock period
RX_CLK duty cycle
RX_CLK peak-to-peak jitter
Rise time RX_CLK (20%–80%)
Fall time RX_CLK (80%–20%)
RCG[9:0] setup time to RX_CLK rising edge
RCG[9:0] hold time to RX_CLK rising edge
shows the TBI receive AC timing diagram.
TBI Receive Clock 1
TBI Receive Clock 0
(TSECn_RX_CLK)
(TSECn_TX_CLK)
TBI Single-Clock Mode AC Specifications
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
Parameter/Condition
RCG[9:0]
Table 34. TBI single-clock Mode Receive AC Timing Specification
Figure 23. TBI Receive AC Timing Diagram
DD
t
t
SKTRX
/TV
TRXH
t
TRDVKH
DD
of 3.3 V ± 5%
t
TRX
t
TRXH
Valid Data
Symbol
t
t
t
t
TRRDV
TRRDX
t
t
t
TRRH
TRRR
TRRF
TRRJ
TRR
t
TRXF
Valid Data
Min
7.5
2.0
1.0
40
—
—
—
t
TRDXKH
t
TRXR
Table
t
TRDVKH
Typ
8.0
34.
50
—
—
—
—
—
t
TRDXKH
Freescale Semiconductor
Max
250
8.5
1.0
1.0
60
—
—
Unit
ns
ps
ns
ns
ns
ns
%