MPC8536DS Freescale, MPC8536DS Datasheet - Page 99

• Manufacturer Part Number: MPC8536DS
• Manufacturer: Freescale

Specifications of MPC8536DS

• Lead Free Status / RoHS Status: Compliant

The other detailed AC requirements of the SerDes Reference Clocks is defined by each interface protocol based on application
usage. See the following sections for detailed information:
2.20.2.4.1 Spread Spectrum Clock
SD1_REF_CLK/SD1_REF_CLK were designed to work with a spread spectrum clock (+0 to -0.5% spreading at 30–33 kHz
rate is allowed), assuming both ends have same reference clock. For better results, a source without significant unintended
modulation should be used.
SD2_REF_CLK/SD2_REF_CLK are not intended to be used with, and should not be clocked by, a spread spectrum clock
source.
2.20.3 SerDes Transmitter and Receiver Reference Circuits
Figure 68
The DC and AC specification of SerDes data lanes are defined in each interface protocol section below (PCI Express, SATA or
SGMII) in this document based on the application usage:
Please note that external AC Coupling capacitor is required for the above three serial transmission protocols with the capacitor
value defined in specification of each protocol section.
Freescale Semiconductor
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Section 2.9.3.2, “AC Requirements for SGMII SD2_REF_CLK and
Section 2.21.2, “AC Requirements for PCI Express SerDes
Section 2.9.3, “SGMII Interface Electrical Characteristics”
Section 2.21, “PCI Express”
Section 2.16, “Serial ATA (SATA)”
shows the reference circuits for SerDes data lane’s transmitter and receiver.
SD n _REF_CLK
SD n _REF_CLK
Figure 67. Single-Ended Measurement Points for Rise and Fall Time Matching
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
Transmitter
Figure 68. SerDes Transmitter and Receiver Reference Circuits
50 Ω
50 Ω
SD1_TXn or
SD2_TXn
SD1_TXn or
SD2_TXn
SD n _REF_CLK
SD n _REF_CLK
Clocks”
SD1_RXn or
SD2_RXn
SD1_RXn or
SD2_RXn
SD2_REF_CLK”
50 Ω
50 Ω
Receiver
High-Speed Serial Interfaces
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