MPC8536DS Freescale, MPC8536DS Datasheet - Page 35

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MPC8536DS

Manufacturer Part Number
MPC8536DS
Description
Manufacturer
Freescale
Datasheet

Specifications of MPC8536DS

Lead Free Status / RoHS Status
Compliant
At recommended operating conditions with GV
MCK[n] cycle time, MCK[n]/MCK[n] crossing
ADDR/CMD output setup with respect to MCK
ADDR/CMD output hold with respect to MCK
MCS[n] output setup with respect to MCK
MCS[n] output hold with respect to MCK
MCK to MDQS Skew
MDQ/MECC/MDM output setup with respect to
MDQS
MDQ/MECC/MDM output hold with respect to
MDQS
MDQS preamble start
2.6.2.2
Table 19
Freescale Semiconductor
contains the output AC timing targets for the DDR2 and DDR3 SDRAM interface.
DDR2 and DDR3 SDRAM Interface Output AC Timing Specifications
Parameter
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
Table 19. DDR SDRAM Output AC Timing Specifications
<= 667 MHz
667 MHz
533 MHz
400 MHz
667 MHz
533 MHz
400 MHz
667 MHz
533 MHz
400 MHz
667 MHz
533 MHz
400 MHz
667 MHz
533 MHz
400 MHz
667 MHz
533 MHz
400 MHz
DD
of 1.8 V ± 5% for DDR2 or 1.5 V ± 5% for DDR3.
Symbol
t
t
t
t
t
t
t
t
t
t
DDKHDS,
DDKHDX,
DDKHMH
DDKHMP
DDKHAS
DDKHAX
DDKHCS
DDKHCX
DDKLDS
DDKLDX
t
MCK
1
1.10
1.48
1.95
1.10
1.48
1.95
1.10
1.48
1.95
1.10
1.48
1.95
–0.6
Min
450
538
700
450
538
700
3.0
Max
0.6
5
DDR2 and DDR3 SDRAM
Unit
ns
ns
ns
ns
ns
ns
ps
ps
ns
Notes
2
3
7
3
7
3
7
3
7
4
7
5
7
5
7
6
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