TXC-03305AIPQ Transwitch Corporation, TXC-03305AIPQ Datasheet - Page 35

• Manufacturer Part Number: TXC-03305AIPQ
• Manufacturer: Transwitch Corporation

Specifications of TXC-03305AIPQ

• Lead Free Status / RoHS Status: Not Compliant

Notes:
1. The transmit clock (XCK) or receive clock (DS3CR) must be present for the microprocessor bus
2. The SEL lead must be brought high for 2 transmit clock cycles before the start of a new write cycle.
A(7-0) address hold time after WR
A(7-0) address setup time before SEL
D(7-0) data valid setup time before WR
D(7-0) data hold time after WR
SEL setup time before WR
WR pulse width
interface to operate. The RDY/DTACK output lead is always driven high when the SEL lead is low,
otherwise it is tri-stated, which corresponds to the behavior of the M13E device.
A(7-0)
D(7-0)
SEL
WR
Parameter
Figure 15. Microprocessor Write Cycle Timing - Intel Interface
t
SU(1)
Symbol
t
t
t
t
SU(1)
SU(2)
t
SU(3)
t
H(1)
H(2)
PW
t
SU(3)
DATA SHEET
- 35 -
Min
0.0
20
20
10
80
5
t
PW
t
SU(2)
Typ
t
H(1)
t
H(2)
212,000
Max
Ed. 4, September 2000
TXC-03305
TXC-03305-MB
Unit
M13X
ns
ns
ns
ns
ns
ns