TXC-03305AIPQ Transwitch Corporation, TXC-03305AIPQ Datasheet - Page 89

• Manufacturer Part Number: TXC-03305AIPQ
• Manufacturer: Transwitch Corporation

Specifications of TXC-03305AIPQ

• Lead Free Status / RoHS Status: Not Compliant

2C (cont.)
Address
2D
4-3
2-1
7-0
Bit
0
IRRXFS1-
IRTXFS1-
IRRXFS0
Reserved
IRTXFS0
Symbol
IRTHIS
Receive PMDL FIFO Interrupt Request: The following table lists the vari-
ous FIFO status indications associated with the receive PMDL FIFO.
These are latched bits that clear when the register is read by the micropro-
cessor. If a bit in this register is set to a 1 and the corresponding interrupt
mask bit in register 35H is set to a 1, then the INT/IRQ lead goes active to
signal an interrupt request to the external microprocessor. When a condi-
tion occurs both bits are updated at once. 00 is never forced by the internal
logic. These bits are only set to 00 when a read is performed.
Transmit PMDL FIFO Interrupt Request: The following table lists the vari-
ous FIFO status indications associated with the transmit PMDL FIFO.
These are latched bits that clear when the register is read by the micropro-
cessor. If a bit in this register is set to a 1 and the corresponding interrupt
mask bit in register 35H is set to a 1, then the INT/IRQ lead goes active to
signal an interrupt request to the external microprocessor. When a condi-
tion occurs both bits are updated at once. 00 is never forced by the internal
logic. These bits are only set to 00 when a read is performed.
Transmit PMDL Interrupt Request: A 1 indicates that the transmit PMDL
FIFO needs servicing, either because the message is completed, or
because the transmit PMDL FIFO transitioned from more than half full to
half full, depending on the THIE control bit setting. This is a latched bit, and
clears when the register is read by the microprocessor. If this bit is set to a
1 and the corresponding interrupt mask bit in register 35H is set to a 1, then
the INT/IRQ lead goes active to signal an interrupt request to the external
microprocessor.
Reserved: These bits are reserved and must always be ignored.
IRRXFS1
IRTXFS1
0
0
1
1
0
0
1
1
IRRXFS0
IRTXFS0
DATA SHEET
- 89 -
0
1
0
1
0
1
0
1
Normal. PMDL FIFO less than half full.
FIFO equal to or more than half full
FIFO full
FIFO overflow
Normal. PMDL FIFO equal to or more than half full
FIFO less than half full
FIFO overflowed (attempt to write to a full FIFO)
FIFO underflowed. Reported only if EOM is not set
when FIFO underflows.
Description
Condition Present
Condition Present
Ed. 4, September 2000
TXC-03305
TXC-03305-MB
M13X