TXC-03305AIPQ Transwitch Corporation, TXC-03305AIPQ Datasheet - Page 74

• Manufacturer Part Number: TXC-03305AIPQ
• Manufacturer: Transwitch Corporation

Specifications of TXC-03305AIPQ

• Lead Free Status / RoHS Status: Not Compliant

TXC-03305-MB
Ed. 4, September 2000
M13X
TXC-03305
Address
0A
0B
08
09
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Reserved
Reserved
Symbol
LBDS3
LBALL
LB25
LB21
LB17
LB13
LB26
LB22
LB18
LB14
LB10
LB27
LB23
LB19
LB15
LB11
LB28
LB24
LB20
LB16
LB12
LB9
LB5
LB1
LB6
LB2
LB7
LB3
LB8
LB4
Receive Loopback Requests: Bit 7, LBALL (all DS1 channels), bits 6-0
(LBn), and registers 09H through 0BH indicate the loopback request
detected. For the M13 format mode, a loopback request is received when
any of the conditions (DS2 C-bit or stuff) are detected five or more times in
succession. The remote loopback selection is determined by the states
written to the 1LBVn bits in register location 20H. A remote loopback
request is cancelled when the normal state of the bit is received five or
more times in succession. In the C-bit parity mode, a remote loopback
request is received by detecting the FEAC connect word five times in suc-
cession, followed by five consecutive receptions of the DS1 channel num-
ber word. A remote loopback request is cleared upon the reception of five
consecutive disconnect FEAC messages followed by the reception of the
DS1 channel number word. The M13X will also respond to the conditions
(DS2 C-bit or stuff) set up by the 1LBVn bits in register location 20H while
in C-bit parity mode. Note: It is possible to have multiple loopbacks set.
Once a loopback request is received or taken down in registers 08H-0BH,
the microprocessor must write the appropriate code to register 1EH to cor-
respondingly set up or take down the loopback in the appropriate DS1
channel.
When detecting loopback requests via the mechanism indicated by the
1LBVn bits in register 20H, the M13X must have DS2 and DS3 frame syn-
chronization. When detecting loopback requests via the FEAC channel, the
M13X must have DS3 frame synchronization and not be receiving DS3 AIS
or DS3 Idle signals. LBALL is valid only in C-bit parity mode.
Receive Loopback Requests: Bits 7 (LBDS3), 6-0 (LBn), and registers
08H, 0AH and 0BH indicate loopback requests sent by the distant end for
either a DS3 loopback or for the DS1 channels indicated. For complete
explanation, see 08H. LBDS3 is valid only in C-bit parity mode.
Reserved: This bit should always be ignored.
Receive Loopback Requests: Bits 6-0 (LBn) and registers 08H, 09H and
0BH indicate loopback requests sent by the distant end for the DS1 chan-
nels indicated. For complete explanation, see 08H.
Reserved: This bit should always be ignored.
Receive Loopback Requests: Bits 6-0 (LBn) and registers 08H through
0AH indicate loopback requests sent by the distant end for the DS1 chan-
nels indicated. For complete explanation, see 08H.
DATA SHEET
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Description