TXC-03305AIPQ Transwitch Corporation, TXC-03305AIPQ Datasheet - Page 87

• Manufacturer Part Number: TXC-03305AIPQ
• Manufacturer: Transwitch Corporation

Specifications of TXC-03305AIPQ

• Lead Free Status / RoHS Status: Not Compliant

* Note: The bits in register 2BH are latched bits, and they all clear to 0 when it is read by the microprocessor. If a bit and
Address
2B*
2A
its corresponding interrupt mask bit in register 34H are both set to a 1, then the INT/IRQ lead goes active to sig-
nal an interrupt request to the external microprocessor. The RISE and FALL bits in register 3FH control whether
these interrupt request bits are set on the entrance or exit of an alarm condition, or both.
6-0
Bit
7
7
6
5
4
3
2
1
0
IRDS2OOFn
IRCERROR
IRC1BZS
IRFMES
IRFCSS
Symbol
IRABTS
(n=7-1)
IRMES
IRCPS
IRFBS
IRPPS
Latched C-bit Status/DS2 Out Of Frame Interrupt Request Bits: The
bits in this register location are interrupt request bits for the alarm/status
bits listed in register location 03H. When a bit in this register and its corre-
sponding interrupt request mask bit in register 33H are both set to 1, the
INT/IRQ lead is driven active. A microprocessor read of the register clears
all set interrupt request bits. The RISE and FALL bits in register 3FH control
whether these interrupt request bits are set on the entrance or exit of an
alarm condition, or both.
FCS Error Counter Saturated Interrupt Request: This bit becomes set
when the RX FCS Error Counter (3BH) saturates.
ABORT Counter Saturated Interrupt Request: This bit becomes set
when the RX ABORT Counter (3CH) saturates.
FEBE Performance/DS3 F-Bit and M-Bit Error Counter Saturated Inter-
rupt Request: This bit becomes set when the FEBE Performance/DS3 F-
bit and M-bit Error Counter (04H) saturates.
C-Bit Parity Performance/Number of Frames Counter Saturated Inter-
rupt Request: This bit becomes set when the C-bit Parity Performance/
Number of Frames Counter (05H) saturates.
P-Bit Parity Performance Counter Saturated Interrupt Request: This bit
becomes set when the P-bit Parity Performance Counter (06H) saturates.
DS3 F-Bits and M-Bits in Error Counter Saturated Interrupt Request:
This bit becomes set when the DS3 F-bits and M-bits in Error Counter
(1BH) saturates.
C1 Bit Equal to Zero Counter Saturated Interrupt Request: This bit
becomes set when the C1 Bit Equal to Zero Counter (22H) saturates.
DS3 M-bits in Error Counter Saturated Interrupt Request: This bit
becomes set when the DS3 M-Bits in Error Counter (23H) saturates.
DATA SHEET
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Description
Ed. 4, September 2000
TXC-03305
TXC-03305-MB
M13X