TXC-03305AIPQ Transwitch Corporation, TXC-03305AIPQ Datasheet - Page 39

• Manufacturer Part Number: TXC-03305AIPQ
• Manufacturer: Transwitch Corporation

Specifications of TXC-03305AIPQ

• Lead Free Status / RoHS Status: Not Compliant

OPERATION
The sections below contain descriptions of the M13X features. In the M13X device, the counters, interrupt
request bits, interrupt mask bits, new control bits, and PMDL FIFO interface will be located at addresses 25H-
3FH.
M13X LEAD
In order to maintain backwards compatibility with the M13E device, a control lead with an internal pull-up,
M13X, has been added. When this lead is set to high, or left floating, all of the M13X functions contained in
address locations 25H-3FH are disabled. This means that:
When the M13X lead is set to low:
Regardless of the setting of the M13X lead, the M13XID0 bit (register 10H, bit 7) bit will always be set to 0. The
1. Saturate, as used throughout this document when referring to a counter, means that a counter stops
at its maximum count and does not roll over to zero when the next count event occurs.
• The PMDL (Path Maintenance Data Link) C-bits are inserted and extracted solely through the exter-
• The internal dejitter buffers (DJBs) are bypassed.
• The external address straps S5-S7 operate as in the M13E device.
• Only the registers defined by the settings of the P0 and P1 leads and straps S5-S7 are accessible.
• All counters are 8 bits long, clear when read, and saturate when a count of FFH is reached.
• The TXFRM lead is operational.
• NEW bit will be set under the conditions that caused the NEW bit to be set in the M13E device.
• The bits in registers 25H-3FH can be used to control, enable/disable, and monitor the M13X func-
• The address strap S5 is ignored.
• Address straps S6 and S7 are enabled to allow the M13X to be mapped to address ranges 00H-3FH,
• The counters become 16 bits in length, clear when read, and saturate
• The TXFRM lead is operational.
• NEW bit in register 1DH does not become set to one again after it is cleared when a continuous con-
nal C-bit interfaces (in C-bit Parity format mode) or by the internal stuffing logic (in M13 format mode).
Any reads from addresses outside of those ranges cause the microprocessor interface of the M13X
to remain tri-stated. Any writes to locations 25H-3FH will not have any effect on device operation. Fur-
thermore, when the P0 and P1 leads are both set to high, registers 20H-3FH are not accessible for
read or write operations.
Namely, the NEW bit becomes set when any five consecutive and identical FEAC messages are
received. The NEW bit will continually be reasserted if it is read and cleared when a continuous con-
stant FEAC message is received.
tions.
40H-7FH, 80H-BFH, or C0H-FFH. When the M13X is mapped to an address range, all accesses to
addresses outside of that range are handled by the M13X as if the SEL chip-select input lead is high.
That is, all read operations cause the microprocessor bus to be tri-stated and write operations will not
have any effect upon any register. Furthermore, when lead P1 is high and P0 is low, the multiplexed
mode of operation is selected, but access to all registers (00H-3FH) is provided. Setting both P1 and
reached. When the low byte of a 16-bit counter is read, the high byte is simultaneously written to a
common high byte register location (3EH). So, in order to read a 16-bit counter, the counter register
is read first to get the low byte, then the common high byte register is read to get the high byte.
stant FEAC message is received.
P0 high is not allowed.
DATA SHEET
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1
when a count of FFFFH is
Ed. 4, September 2000
TXC-03305
TXC-03305-MB
M13X