82V2081PPG8 IDT, Integrated Device Technology Inc, 82V2081PPG8 Datasheet - Page 15

• Manufacturer Part Number: 82V2081PPG8
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82V2081PPG8

• Number Of Transceivers: 1
• Screening Level: Industrial
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Compliant

SINGLE CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
3
3.1
software control mode supports Serial Control Interface, Motorola Multi-
plexed Control Interface and Intel Multiplexed Control Interface. The Con-
trol mode is selected by MODE1 and MODE0 pins as follows:
•
•
•
3.2
the T1E1 bit (GCF, 02H). In E1 application, the T1E1 bit (GCF, 02H) should
be set to ‘0’. In T1/J1 application, the T1E1 bit should be set to ‘1’.
by PULS[3:0] pins. These pins also determine transmit pulse template and
internal termination impedance. Refer to
SUMMARY
3.3
Jitter Attenuator, a Waveform Shaper, a set of LBOs, a Line Driver and a
Programmable Transmit Termination.
3.3.1
and TDN pin. In E1 mode, TCLK is a 2.048 MHz clock. In T1/J1 mode, TCLK
is a 1.544 MHz clock. If TCLK is missing for more than 70 MCLK cycles, an
interrupt will be generated if it is not masked.
edge of TCLK. The active edge of TCLK can be selected by the TCLK_SEL
bit (TCF0, 05H). And the active level of the data on TD/TDP and TDN can
be selected by the TD_INV bit (TCF0, 05H). In hardware control mode, the
falling edge of TCLK and the active high of transmit data are always used.
ways: Single Rail and Dual Rail. In Single Rail mode, only TD pin is used
for transmitting data and the T_MD[1] bit (TCF0, 05H) should be set to ‘0’.
In Dual Rail Mode, both TDP pin and TDN pin are used for transmitting data,
the T_MD[1] bit (TCF0, 05H) should be set to ‘1’.
The IDT82V2081 can be configured by software or by hardware. The
When the chip is configured by software, T1/E1/J1 mode is selected by
When the chip is configured by hardware, T1/E1/J1 mode is selected
The transmit path of IDT82V2081 consists of an Encoder, an optional
The transmit path system interface consists of TCLK pin, TD/TDP pin
Transmit data is sampled on the TD/TDP and TDN pins by the active
The transmit data from the system side can be provided in two different
The serial microcontroller Interface consists of CS, SCLK, SCLKE,
SDI, SDO and INT pins. SCLKE is used for the selection of active
edge of SCLK.
The parallel Multiplexed microcontroller Interface consists of CS,
AD[7:0], DS/RD, R/W/WR, ALE/AS, ACK/RDY and INT pins.
Hardware interface consists of PULS[3:0], THZ, RCLKE, LP[1:0],
PATT[1:0], JA[1:0], MONT, TERM, EQ, RPD, MODE[1:0] and
RXTXM[1:0]. Refer to
for details about hardware control.
00
01
10
11
FUNCTIONAL DESCRIPTION
CONTROL MODE SELECTION
T1/E1/J1 MODE SELECTION
TRANSMIT PATH
TRANSMIT PATH SYSTEM INTERFACE
for details.
Hardware interface
Serial Microcontroller Interface.
Parallel –Multiplexed -Motorola Interface
Parallel –Multiplexed -Intel Interface
5 HARDWARE CONTROL PIN SUMMARY
Control Interface mode
5 HARDWARE CONTROL PIN
15
3.3.2
selected to be a B8ZS encoder or an AMI encoder by setting T_MD[0] bit
(TCF0, 05H).
figured to be a HDB3 encoder or an AMI encoder by setting T_MD[0] bit
(TCF0, 05H).
T_MD[1] is ‘1’), the Encoder is by-passed. In Dual Rail mode, a logic ‘1’ on
the TDP pin and a logic ‘0’ on the TDN pin results in a negative pulse on the
TTIP/TRING; a logic ‘0’ on TDP pin and a logic ‘1’ on TDN pin results in a
positive pulse on the TTIP/TRING. If both TDP and TDN are high or low,
the TTIP/TRING outputs a space (Refer to
path can be selected by setting RXTXM1 and RXTXM0 pins. Refer to
HARDWARE CONTROL PIN SUMMARY
3.3.3
before sending it. The first is to use preset pulse templates for short haul
application, the second is to use LBO (Line Build Out) for long haul appli-
cation and the other way is to use user-programmable arbitrary waveform
template.
the related registers.
PULS[3:0] pins. Refer to
details.
3.3.3.1 Preset Pulse Templates
the G.703 and the measuring diagram is shown in Figure-4. In internal
impedance matching mode, if the cable impedance is 75 Ω, the PULS[3:0]
bits (TCF1, 06H) should be set to ‘0000’; if the cable impedance is 120 Ω,
the PULS[3:0] bits (TCF1, 06H) should be set to ‘0001’. In external imped-
ance matching mode, for both E1/75 Ω and E1/120 Ω cable impedance,
PULS[3:0] should be set to ‘0001’.
In Single Rail mode, when T1/J1 mode is selected, the Encoder can be
In Single Rail mode, when E1 mode is selected, the Encoder can be con-
In both T1/J1 mode and E1 mode, when Dual Rail mode is selected (bit
In hardware control mode, the operation mode of receive and transmit
The IDT82V2081 provides three ways of manipulating the pulse shape
In software control mode, the pulse shape can be selected by setting
In hardware control mode, the pulse shape can be selected by setting
For E1 applications, the pulse shape is shown in
PULSE SHAPER
Figure-3 E1 Waveform Template Diagram
ENCODER
1 .2 0
1 .0 0
0 .6 0
0 .4 0
-0 .2 0
0 .8 0
0 .2 0
0 .0 0
- 0 .6
-0 .4
5 HARDWARE CONTROL PIN SUMMARY
-0 .2
T im e in U n it In te rv a ls
0
TD/TDP, TDN Pin
for details.
TEMPERATURE RANGES
0 .2
Figure-3
0 .4
INDUSTRIAL
Description).
according to
0 .6
for
5