82V2081PPG8 IDT, Integrated Device Technology Inc, 82V2081PPG8 Datasheet - Page 24

• Manufacturer Part Number: 82V2081PPG8
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82V2081PPG8

• Number Of Transceivers: 1
• Screening Level: Industrial
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Compliant

SINGLE CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
3.6
3.6.1
nal level and pulse density of the received signal on RTIP and RRING.
when the signal level is less than Q dB below nominal for N consecutive
pulse intervals. Here N is defined by LAC bit (MAINT0, 0DH). LOS will be
declared by pulling LOS pin to high (LOS=1) and LOS interrupt will be gen-
erated if it is not masked.
when the signal level is greater than P dB below nominal and has an aver-
age pulse density of at least 12.5% for M consecutive pulse intervals, start-
ing with the receipt of a pulse. Here M is defined by LAC bit (MAINT0, 0DH).
LOS status is cleared by pulling LOS pin to low.
Table-17 LOS Declare and Clear Criteria for Short Haul Mode
(observing windows= M)
The Loss of Signal Detector monitors the amplitude of the incoming sig-
• LOS declare (LOS=1)
A LOS is detected when the incoming signal has “no transitions”, i.e.,
• LOS clear (LOS=0)
The LOS is cleared when the incoming signal has “transitions”, i.e.,
1=T1/J1
T1E1
0=E1
density=OK
signal level>P
LOS AND AIS DETECTION
LOS DETECTION
Control bit
Figure-12 LOS Declare and Clear
0=T1.231
1=I.431
0=G.775
1=I.431/ETSI
LAC
LOS=0
Level < 800 mVpp
N=175 bits
Level < 800 mVpp
N=1544 bits
Level < 800 mVpp
N=32 bits
Level < 800 mVpp
N=2048 bits
LOS=1
signal level<Q
(observing windows= N)
LOS declare threshold
24
while P=Q+200 mVpp (200 mVpp is the LOS level detect hysteresis).
0BH), while P=Q+4 dB (4 dB is the LOS level detect hysteresis). The
LOS[4:0] default value is 10101 (-46 dB).
if the IDT82V2081 operates in long haul mode. It is -46dB (E1) and -38dB
(T1/J1).
G.775 and ETSI 300233/I.431 for E1 mode. The criteria can be selected
by LAC bit (MAINT0, 0DH) and T1E1 bit (GCF, 02H).
both short haul and long haul application.
at the RTIP/RRING side and output recovered clock (but the quality of the
output clock can not be guaranteed when the input level is lower than the
maximum receive sensitivity) when AISE bit (MAINT0, 0DH) is 0; or output
All Ones as AIS when AISE bit (MAINT0, 0DH) is 1. In this case, RCLK out-
put is replaced by MCLK.
bit (MAINT0, 0DH) is 1. The All Ones pattern uses MCLK as the reference
clock.
• LOS detect level threshold
In short haul mode, the amplitude threshold Q is fixed on 800 mVpp,
In long haul mode, the value of Q can be selected by LOS[4:0] bit (RCF1,
When the chip is configured by hardware, the LOS detect level is fixed
• Criteria for declare and clear of a LOS detect
The detection supports the ANSI T1.231 and I.431 for T1/J1 mode and
Table-17
• All Ones output during LOS
On the system side, the RDP/RDN will reflect the input pulse “transition”
On the line side, the TTIP/TRING will output All Ones as AIS when ATAO
LOS indicator is always active for all kinds of loopback modes.
and
Level > 1 Vpp
M=128 bits
12.5% mark density
<100 consecutive zeroes
Level > 1 Vpp
M=128 bits
12.5% mark density
<100 consecutive zeroes
Level > 1 Vpp
M=32 bits
12.5% mark density
<16 consecutive zeroes
Level > 1 Vpp
M=32 bits
12.5% mark density
<16 consecutive zeroes
Table-18
summarize LOS declare and clear criteria for
LOS clear threshold
TEMPERATURE RANGES
INDUSTRIAL