HFIXF1110CC Intel, HFIXF1110CC Datasheet - Page 64

• Manufacturer Part Number: HFIXF1110CC
• Manufacturer: Intel

Specifications of HFIXF1110CC

• Number Of Transceivers: 1
• Screening Level: Commercial
• Mounting: Surface Mount
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Lead Free Status / RoHS Status: Not Compliant

Intel
5.2.2
5.2.2.1
07-Oct-2005
64
®
Figure 13. DIP-4 Calculation Algorithm
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
Start-Up Parameters
CALENDAR_LEN
CALENDAR_LEN specifies the length of each calendar sequence. As the IXF1110IXF1110 MAC
is a 10-port device, CALENDAR_LEN is fixed at 10 for both TX and RX data paths.
2
3
4
5
6
7
8
9
15
Intel
3
1
1
0
1
0
0
0
0
1
1
1
1
1
0
0
0
0
14
0
1
0
0
1
0
0
1
1
1
1
1
1
0
0
0
0
2
®
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
13
0
0
0
0
1
0
0
1
0
1
0
0
1
1
1
0
1
1
12
0
1
0
1
1
0
1
1
1
1
0
0
0
0
0
0
0
0
11
0
0
1
0
0
0
0
0
0
0
1
1
1
0
DIP4 parity bits
(DIP4[3:0])
Order Number: 250210, Revision: 009
DIP4[3] = DIP16[15]
DIP4[2] = DIP16[14]
DIP4[1] = DIP16[13]
DIP4[0] = DIP16[12]
10
0
0
0
0
0
0
0
0
0
0
0
0
0
0
9
0
0
1
0
1
0
0
0
0
0
0
0
0
0
8
0
0
0
0
0
0
0
1
0
0
1
1
1
0
7
1
1
1
0
0
1
0
1
0
1
1
8-bit parity sum
6
0
0
1
0
0
0
0
1
0
0
1
DIP16[11]
DIP16[10]
DIP16[9]
DIP16[8]
5
1
1
1
0
1
0
1
1
0
0
1
4
1
1
1
0
1
0
1
1
0
0
0
3
w
0
0
0
1
0
0
0
0
a
1
DIP16[7]
DIP16[6]
DIP16[5]
DIP16[4]
2
x
1
0
0
1
0
1
0
0
b
0
1
y
1
0
1
1
1
1
0
0
c
0
DIP16[3]
DIP16[2]
DIP16[1]
DIP16[0]
0
z
0
0
0
0
0
0
0
0
d
1
16-bit parity sum
(DIP16[15:0])
to 2
to 3
to 4
to 5
to 6
to 7
to 8
to 9
word of incoming burst
word of incoming burst
word of incoming burst
Each bit of this 16-bit parity sum is the
result of a XOR operation along the
corresponding dashed line.
word of incoming burst
word of incoming burst
word of incoming burst
word of incoming burst
control word: included in parity
calculations (contains the results of
parity for the 8 SPI-4 Phase II data
words above and this control word)
control word: not included in
parity calculations below
1st SPI-4 Phase II data
word of incoming burst
2nd SPI-4 Phase II data
3rd SPI-4 Phase II data
4th SPI-4 Phase II data
5th SPI-4 Phase II data
6th SPI-4 Phase II data
7th SPI-4 Phase II data
8th SPI-4 Phase II data
a, b, c and d are all set
to 1 during encoding.
A9040-01
Datasheet