CY7C924ADX-AI Cypress Semiconductor Corp, CY7C924ADX-AI Datasheet - Page 11

• Manufacturer Part Number: CY7C924ADX-AI
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C924ADX-AI

• Number Of Transceivers: 1
• Data Rate: 622Mbps
• Operating Supply Voltage (typ): 5V
• Supply Current (max): 250mA
• Screening Level: Industrial
• Pin Count: 100
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

Document #: 38-02008 Rev. *E
Pin Descriptions
CY7C924ADX HOTLink Transceiver
50
52, 51
1
89, 90,
81, 82
97
78
94, 93,
86, 85
2
4,5
100
Number
Analog I/O and Control
Pin
BYTE8/10*
RESET*[1:0]
TEST*
OUTA±
OUTB±
CURSETA
CURSETB
INA±
INB±
A/B*
DLB[1:0]
CARDET
Name
(continued)
Static control input
TTL levels Normally
wired HIGH or LOW
TTL input,
TTL input,
asynchronous.
Normally wired HIGH
PECL-compatible
differential outputs
Analog input
Analog input
PECL-compatible
differential inputs
TTL input,
asynchronous,
Internal Pull Up
TTL input,
asynchronous,
Internal Pull Down
PECL-compatible
input, asynchronous
I/O Characteristics
Parallel Data Character Size Select. Selects the input data character width.
When BYTE8/10* is HIGH and ENCBYP* is HIGH, the device is in 8 bit mode
and the data is encoded using the 8B/10B code rules found in
page 51
is LOW, the 10 parallel data bits pass directly to or from the serial stream
without encoding or decoding.
When BYTE8/10* is LOW, the part is in 10 bit mode. If the encoder is enabled
(ENCBYP* is HIGH), the part passes the 10 parallel bits to the byte stuffer and
encoder. When the encoder is disabled (ENCBYP* is LOW), the 12 parallel
data bits pass directly to or from the serial stream without encoding or
decoding.
For affected pin groupings and function see
on page
If the FIFOs are BYPASSED and Encoding is enabled (FIFOBYP* = LOW and
ENCBYP* = HIGH), BYTE8/10* MUST BE HIGH.
Global Logic Reset. These inputs are pulsed LOW for one or more REFCLK
periods to reset the internal logic. They must be tied together or driven concur-
rently to ensure a valid reset.
Factory Test Mode Select. Used to force the part into a diagnostic test mode
for factory ATE test. This pin is tied HIGH during normal operation.
Differential Serial Data Outputs. These PECL-compatible outputs are
capable of driving terminated transmission lines or commercial fiber optic
transmitter modules. An unused output pair may be powered down by leaving
the outputs unconnected and strapping the associated CURSETx pin to V
Current-set Resistor Input for OUTA±. A precision resistor is connected
between this input and a clean ground to set the output differential amplitude
and currents for the OUTA± differential driver.
Current-set Resistor Input for OUTB±. A precision resistor is connected
between this input and a clean ground to set the output differential amplitude
and currents for the OUTB± differential driver.
Differential Serial Data Inputs. These inputs accept the serial data stream
for deserialization and decoding. Only one serial stream at a time may be fed
to the receiver PLL to extract the data content. This stream is selected using
the A/B* input. These inputs may also be routed to the OUTB± serial outputs
using the DLB[1:0] inputs.
Receive Data Input Selector. Determines which external serial bit stream is
passed to the receiver clock and data recovery circuit.
Loopback Select Inputs. Selects connections between serial inputs and
outputs. Controls diagnostic loopback and serial loopthrough functions. See
Table 3 on page 17
Carrier Detect Input. Allows an external device to signify that a valid signal
is being presented to the high speed PECL-compatible input buffers, as is
typical on an Optical Module. When CARDET is deasserted LOW, the LFI*
indicator asserts LOW signifying a Link Fault. This input can be tied to V
copper media applications.
and
25.
Table 12 on page
for details.
Signal Description
55. When BYTE8/10* is HIGH and ENCBYP*
Table 1 on page 13
CY7C924ADX
Page 11 of 58
Table 11 on
and
Table 8
DD
DD
for
.
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