CY7C924ADX-AI Cypress Semiconductor Corp, CY7C924ADX-AI Datasheet - Page 37

• Manufacturer Part Number: CY7C924ADX-AI
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C924ADX-AI

• Number Of Transceivers: 1
• Data Rate: 622Mbps
• Operating Supply Voltage (typ): 5V
• Supply Current (max): 250mA
• Screening Level: Industrial
• Pin Count: 100
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

Document #: 38-02008 Rev. *E
(K28.3) special code is sent. These special codes may be
used to force a similar signal transition on the RXINT output of
an attached CY7C924ADX HOTLink Receiver.
This input may be used to transport a low data rate signal (like
a serial RS-232/UART signal) across the interface, without any
significant impact on the actual data being transported across
the link. It may also be used to transparently propagate FIFO
flow control information across the link by directly connecting
the RXHALF* flag of the local receiver to the TXINT of the local
transmitter. The RXINT at the remote end of the link can then
be connected to the TXHALT* input to halt data transfers at the
remote end of the link until the local Receive FIFO has suffi-
cient room to continue.
Asynchronous Byte-Packed
Asynchronous byte-packed mode contains the same features
as asynchronous encoded, but with support for 10-bit source
data. This data is byte-packed through the 8B/10B encoder to
deliver the data across the interface. This mode is enabled
when FIFOBYP* and ENCBYP* are HIGH and BYTE8/10* is
LOW.
When sending extended commands, the larger 10-bit
character size enlarges the extended command space to 1024
(2
Asynchronous Pre-encoded
In Asynchronous pre-encoded modes, the Transmit FIFO is
enabled and the Encoder is disabled (FIFOBYP* is HIGH and
ENCBYP* is LOW). This means that all words clocked into the
input register are written to the Transmit FIFO before being
sent to the Serializer. The Serializer operates synchronous to
REFCLK to generate the serial data bit-clock. SPDSEL and
RANGESEL determine whether REFCLK is multiplied by 10,
5 or 2.5 (if BYTE8/10* is HIGH) or 3, 6 or 12 (if BYTE8/10* is
LOW). In this mode the TXINT and TXHALT* inputs are used
as part of the 10-bit input character. TXSVS, TXSOC and
TXSTOP* are still available.
These modes are usually used for products containing
external encoders or scramblers, that must meet specific
protocol requirements. The host system must assert TXEN*
and provide new data at every rising edge of TXCLK to
maintain the data stream (without overfilling the Transmit
FIFO). If the Transmit FIFO ever goes empty, the Serializer is
loaded with an alternating disparity string of C5.0 (K28.5) sync
characters (when BYTE8/10* is HIGH) or the bit pattern
0110000100011 (when BYTE8/10* is LOW).
This insertion can be an issue for some system implementa-
tions. If the remote receiver is configured to decode 8B/10B
coded characters, it will probably detect running disparity
errors because the bypassed Encoder is not able to track the
running disparity of the previously transmitted character.
However, since these pre-encoded modes are generally used
with alternate forms of scrambling or encoding, for these appli-
cations this disparity is not generally an issue.
To maintain a data stream without adding these C5.0 SYNC
codes, it is necessary that the Transmit FIFO be loaded at the
same speed or faster than the rate that data is read from that
FIFO.
10
) possible commands codes.
CY7C924ADX HOTLink Receive-Path Operating
Mode Descriptions
The HOTLink Receiver can be configured into several
operating modes, each providing different capabilities and
fitting different reception needs. These modes are selected
using the FIFOBYP*, ENBYP* and BYTE8/10* inputs on the
CY7C924ADX Transceiver. These modes can be reduced to
five primary classes:
In all these modes, serial data is received at one of the differ-
ential line receiver inputs and routed to the Deserializer and
Framer. The PLL in the clock and data recovery block is used
to extract a bit-rate clock from the transitions in the data
stream, and uses that clock to capture bits from the serial
stream. These bits are passed to the Deserializer where they
are formed into 10- or 12-bit characters.
To align the incoming bit stream to the proper character bound-
aries, the Framer must be enabled by asserting RFEN HIGH.
The Framer logic-block checks the incoming bit stream for the
unique pattern that defines the character boundaries. This
logic filter looks for the ANSI X3.230 symbol defined as a
“Special Character Comma” (K28.5 or C5.0). Once a K28.5 is
found, the Framer captures the offset of the data stream from
the present character boundaries, and resets the boundary to
reflect this new offset, thus framing the data to the correct
character boundaries.
Since noise induced errors can cause the incoming data to be
corrupted, and since many combinations of corrupt and legal
data can create and aliased K28.5, the framer may also be
disabled by setting RFEN LOW.
An option exists in the framer to require multiple K28.5
characters, meeting specific criteria, before the character
boundaries are reset. This multi-byte mode of the Framer is
enabled by keeping RFEN asserted HIGH for greater than
2048 character clock cycles. For multi-byte framing, the
receiver must find a pair of K28.5 characters, both on identical
10-bit boundaries, within a 5-character span (50 bits) before it
shifts its framing boundaries. This option greatly reduces the
probability of framing to aliased K28.5 characters while still
allowing many links to maintain synchronization.
Synchronous Decoded
In these modes, the Receive FIFO is bypassed, while the
10B/8B Decoder is enabled (FIFOBYP* is LOW and
ENCBYP* is HIGH). Framed characters output from the
Deserializer are decoded, and passed direct to the Receive
Output Register. The Deserializer operates synchronous to
the recovered bit-clock, which is divided by 10 generate the
output RXCLK clock. In this mode the RXRST* input is not
interpreted and may be biased either HIGH or LOW.
These modes are usually used for products that must meet
specific protocol requirements. New decoded characters are
provided at the RXDATA outputs once every rising edge of
RXCLK. When RXEMPTY* is deasserted along with the data,
• Synchronous Decoded
• Synchronous Undecoded
• Asynchronous Decoded
• Asynchronous Byte-packed
• Asynchronous Undecoded.
CY7C924ADX
Page 37 of 58
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