CY7C924ADX-AI Cypress Semiconductor Corp, CY7C924ADX-AI Datasheet - Page 43

• Manufacturer Part Number: CY7C924ADX-AI
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C924ADX-AI

• Number Of Transceivers: 1
• Data Rate: 622Mbps
• Operating Supply Voltage (typ): 5V
• Supply Current (max): 250mA
• Screening Level: Industrial
• Pin Count: 100
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

Document #: 38-02008 Rev. *E
Device Selection
The concept of selection is used to control the access to the
transmit and receive parallel-data ports of the device. There
are three primary types of selection:
In addition to these normal selection types, there are two
additional sequences that are used to control the internal
Transmit and Receive FIFOs reset operations, and to control
read/write access to the Serial Address Register:
Of these operations, the transmit data selection and transmit
reset sequence are mutually exclusive and cannot exist at the
same time. The receive data selection and receive reset
sequence are also mutually exclusive and cannot exist at the
same time. Either transmit operation can exist at the same
time as either receive operation.
All normal forms of selection require that an Address Match
condition must exist (AM* sampled LOW) either at the same
Notes
26. Signals labeled in italics are internal to the CY7C924ADX.
27. Signals shown as dotted lines represent the differences in timing and active state of signals when operated in Cascade Timing.
• Transmit data selection (with and without internal Transmit
• Receive data selection (with and without internal Receive
• Continuous selection (for either or both transmit and receive
• Transmit reset sequence
• Receive reset sequence (includes access to the Serial
FIFO)
FIFO)
interfaces)
Address Register)
(Cascade Timing)
(UTOPIA Timing)
Tx_Selected
Tx_Match
TXFULL*
TXDATA
TXDATA
TXRST*
TXCLK
TXEN*
AM*
[26]
[26]
Figure 9. Transmit Selection with Transmit FIFO Enabled
Note 27
Note 27
Not Full
time as the selection control signal being sampled asserted,
or one or more clock cycles prior to the selection control signal
being sampled asserted.
Transmit Data Selection
Asynchronous With UTOPIA Timing and Control
(Transmit FIFO Enabled)
When AM* is sampled LOW and TXRST* is sampled HIGH by
the rising edge of TXCLK, a Tx_Match condition is generated.
This Tx_Match condition continues until AM* is sampled HIGH
or TXRST* is sampled LOW at the rising edge of TXCLK.
When a Tx_Match (or Tx_RstMatch) condition is present, the
TXEMPTY* and TXFULL* output drivers are enabled. When a
Tx_Match (or Tx_RstMatch) condition is not present, these
same drivers are disabled (High-Z).
The selection state of the Transmit FIFO is entered when a
Tx_Match condition is present, and TXEN* transitions from
HIGH to LOW. Once selected, the Transmit FIFO remains
selected until TXEN* is sampled HIGH by the rising edge of
TXCLK. In the selected state, data present on the TXDATA
inputs is captured and stored in the Transmit FIFO. This
transmit interface selection process is shown in
the first TXEN* assertion, the TX_Match condition is not yet
present so the Transmitter is not selected. However, the
second TXEN* assertion meets this requirement and the
Transmitter selection is successful.
Not Full
D1
D2
D1
D3
D2
D3
CY7C924ADX
Page 43 of 58
Figure
9. For
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