CY7C924ADX-AI Cypress Semiconductor Corp, CY7C924ADX-AI Datasheet - Page 17

• Manufacturer Part Number: CY7C924ADX-AI
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C924ADX-AI

• Number Of Transceivers: 1
• Data Rate: 622Mbps
• Operating Supply Voltage (typ): 5V
• Supply Current (max): 250mA
• Screening Level: Industrial
• Pin Count: 100
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

Document #: 38-02008 Rev. *E
Transmit Shifter
The Transmit Shifter accepts 10 bit or 12 bit parallel data from
the Encoder block once each character time, and shifts it out
the serial interface output buffers using a PLL-multiplied bit
clock. This bit clock runs at 2.5, 5, or 10 times the REFCLK
rate (3, 6, or 12 times when BYTE8/10* and ENCBYP* are
LOW) as selected by RANGESEL and SPDSEL (see
on page
PLL control timing for the parallel transfer, which is not affected
by signal levels or timing at the input pins.
Bits in each character shift out LSB first, as required by ANSI
and IEEE standards for 8B/10B coded serial data streams.
Routing Matrix
The Routing Matrix is a set of precision multiplexers that allow
various combinations of Transmit Shifter, buffered INA± or
INB± serial line receiver inputs, or a reclocked serial line
receiver input to be transmitted from the OUTB± serial data
outputs. The signal routing for the transmit serial outputs is
controlled primarily by the DLB[1:0] inputs as listed in
The level restored (10b) and reclocked (11b) settings make
use of one of the transmit data outputs. When configured for
level restored or reclocked data, the selected input is retrans-
mitted on OUTB±. The level restored connection simply
buffers the input signal allowing a “bus like” connection to be
constructed without concern for multidrop PECL compatible
signal layout issues.
The reclocked connection buffers a PLL filtered copy of the
selected input data stream. This removes most of the high
frequency jitter that accumulates on a signal when sent over
long transmission lines. Because the retransmitted data is
clocked by the recovered clock, the data can suffer from jitter
peaking when communicated through several PLLs.
For more details on these and LOOPTX reclocking options,
see
Serial Line Drivers
The serial interface PECL compatible Output Drivers (ECL
referenced to +5V) are the transmission line drivers for the
serial media. OUTA± receives its data directly from the
transmit shifter, while OUTB± receives its data from the
Routing Matrix. These two outputs (OUTA± and OUTB±) can
connect directly to +5V optical modules, and can also directly
drive DC or AC coupled transmission lines.
The PECL compatible Output Drivers can be viewed as
programmable current sources. The output current and the
load impedance Z
desired output voltage swing is therefore controlled by the
current set resistor R
Different R
impedance/amplitude combinations. The output swing is
designed to center around V
externally biased to V
When the interconnect and load are viewed as a differential
transmission line, the absolute voltage V
ential load impedance are used to calculate the value of
R
impedance on the driver, and by the resistance of the R
resistor for that driver, as listed in
CURSET
“Serial Line Receivers” on page
. This amplitude relationship is controlled by the load
18). The counter and dividers in the Clock Multiplier
CURSET
LOAD
values are required for different line
DD
CURSET
− 1.33V.
determine the output voltage. The
DD
− 1.33V. Each output must be
associated with that driver.
Equation
20.
ODIF
1.
and the differ-
Table 3
CURSET
Table 4
Table 3. Transmit Data Routing Matrix
In
output of the differential driver when that output is driving HIGH
and LOW, Z
complement outputs of the driver. With a known load
impedance and a desired signal swing, it is possible to
calculate the value of the associated CURSETA or CURSETB
resistor that sets this current.
Unused differential output drivers must be left open, and can
reduce their power dissipation by connecting their respective
CURSETx input to V
Transmit PLL Clock Multiplier
The Transmit PLL Clock Multiplier accepts an external clock at
the REFCLK input, and multiples that clock by 2.5, 5, or 10 (3,
6, or 12 when BYTE8/10* is LOW and the encoder is disabled)
to generate a bit rate clock for use by the transmit shifter. It
also provides a character rate clock used by the Transmit
Controller state machine.
The clock multiplier PLL can accept a REFCLK input between
8.33 MHz and 40 MHz, however, this clock range is limited by
R
DLB[1] DLB[0]
CURSET
Equation
0
0
1
1
=
1, V
LOAD
90 Z
----------------------------- -
0
1
0
1
V
×
ODIF
ODIF
is the differential load between the true and
LOAD
A/B*
A/B*
A/B*
A/B*
INB
INA
INB
INA
INB
INA
INB
INA
DD
is the difference in voltage levels at one
.
TRANSMIT
TRANSMIT
TRANSMIT
TRANSMIT
SHIFTER
SHIFTER
SHIFTER
SHIFTER
Data Connections
RECEIVE
CY7C924ADX
RECEIVE
RECEIVE
PLL
RECEIVE
PLL
PLL
PLL
Page 17 of 58
OUTA
OUTA
OUTA
OUTA
OUTB
OUTB
OUTB
OUTB
Eq. 1
[+] Feedback