CY7C924ADX-AI Cypress Semiconductor Corp, CY7C924ADX-AI Datasheet - Page 21

• Manufacturer Part Number: CY7C924ADX-AI
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C924ADX-AI

• Number Of Transceivers: 1
• Data Rate: 622Mbps
• Operating Supply Voltage (typ): 5V
• Supply Current (max): 250mA
• Screening Level: Industrial
• Pin Count: 100
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

Document #: 38-02008 Rev. *E
for C5.0 (K28.5) characters at all possible bit positions. The
location of this character in the data stream is used to
determine the character boundaries of all following characters.
The framer operates in one of three different modes, as
selected by the RFEN input. When RFEN is first asserted
(HIGH), the framer is allowed to reset the internal character
boundaries on any detected C5.0 character.
Random errors that occur in the serial data can corrupt some
data patterns into a bit pattern identical to a K28.5, and thus
cause an erroneous data-framing error. To prevent this, the
CY7C924ADX provides a multi-byte framer that is enabled
once RFEN has been HIGH for greater than 2048 character.
This requires two C5.0 characters within a span of five
characters, with both C5.0 characters located on identical
10-bit character boundary locations, before the framer is
allowed to reset the internal character boundary. This
multi-byte framing option greatly reduces the possibility of
erroneously reframing to an aliased K28.5 character.
If RFEN is LOW, the framer is disabled and no changes are
made to character boundaries.
The framer in the CY7C924ADX operates by shifting the
internal character position to align with the character clock.
This ensures that the recovered clock does not contain any
significant phase changes/hops during normal operation or
framing, and allows the recovered clock to be replicated and
distributed to other circuits using PLL-based logic elements.
Decoder Block
The decoder logic block performs two primary functions:
decoding the received transmission characters back into Data
and Special Character codes, and comparing generated BIST
patterns with received characters to permit at-speed link and
device testing.
10B/8B Decoder
The framed parallel output of the Deserializer is passed to the
10B/8B Decoder where, if the Decoder is enabled, it is trans-
formed from a 10-bit transmission character back to the
original Data and Special Character codes. This block uses the
standard decoder patterns in Tables 11 and 12 of this data
sheet. Data patterns are indicated by a LOW on RXSC/D*, and
Special Character codes are indicated by a HIGH. Invalid patterns
or disparity errors are signaled as errors by a HIGH on RXRVS, and
by specific Special Character codes.
If the Decoder is bypassed and BYTE8/10* is HIGH, the ten
(10) data bits of each transmission character are passed
unchanged from the framer to the Pipeline Register.
When the Decoder is bypassed and BYTE8/10* is LOW, the
twelve (12) data bits of each transmission character are
passed unchanged from the framer to the Pipeline Register.
BIST LFSR
The output register of the Decoder block is normally used to
accumulate received characters for delivery to the Receive
Formatter
(RXBISTEN* is LOW), this register becomes a signature
pattern generator and checker by logically converting to a
Linear Feedback Shift Register (LFSR). When enabled, this
block.
When
configured
for
BIST
mode
LFSR generates a 511-character sequence that includes all
Data and Special Character codes, including the explicit
violation symbols.
pseudo-random sequence that can be matched to an identical
LFSR in the Transmitter. When synchronized with the received
data stream, it checks each character in the Decoder with each
character generated by the LFSR and indicates compare
errors at the RXRVS output of the Receive Output Register.
The LFSR is initialized by the BIST hardware to the BIST loop
start code of D0.0 (D0.0 is sent only once per BIST loop). Once
the start of the BIST loop has been detected by the receiver,
RXRVS is asserted for pattern mismatches between the
received characters and the internally generated character
sequence. Code rule violations or running disparity errors that
occur as part of the BIST loop do not cause an error indication.
RXFULL* pulses asserted for one RXCLK cycle per BIST loop and
can be used to check test pattern progress.
The specific patterns checked by the receiver are described in
detail in the Cypress application note “HOTLink Built-In
Self-Test.” The sequence compared by the CY7C924ADX is
identical to that in the HOTLink CY7B933 receiver and the
HOTLink II family of devices CYP(V)15G0x0x, allowing
interoperable systems to be built when used at compatible
serial signaling rates.
If a large number of errors are detected, the receive BIST state
machine aborts the compare operations and resets the LFSR
to the D0.0 state to look for the start of the BIST sequence
again.
Receive Formatter
The Receive Formatter performs three primary functions:
Receive Data Formatting
The protocol enhancements of the transmit path are mirrored
in the receive path logic. The majority of these enhancements
require that the Receive FIFO be enabled to allow the
CY7C924ADX to manage the data stream. In addition to the
standard 10B/8B decoding used for character reception and
recovery, the CY7C924ADX also supports:
All of these capabilities are supported for both 8- and 10-bit
character sizes, and are made possible through use of the
RXSOC bit. RXSOC is generated upon reception of the C8.0,
C9.0, or C10.0 Special Character codes, in those modes
where both the Receive FIFO and the Decoder are enabled.
The entries in
RXRVS bits are formatted to indicate the reception of specific
characters and character combinations. Normal Data and
Special Character code characters are indicated by RXSOC
• Data formatting
• Address matching
• Byte-unpacking
• Marking of packet or cell boundaries using RXSOC
• An expanded control/command character set
• Ability to accept or discard data based on an embedded
• The ability to filter receive data of non-essential information
address
Table 6
show how the RXSOC, RXSC/D*, and
This provides a predictable but
CY7C924ADX
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