L-FW802B-DB LSI, L-FW802B-DB Datasheet - Page 2

• Manufacturer Part Number: L-FW802B-DB
• Manufacturer: LSI

Specifications of L-FW802B-DB

• Lead Free Status / RoHS Status: Compliant

FW802B Low-Power PHY IEEE 1394A-2000
Two-Cable Transceiver/Arbiter Device
Contents
Distinguishing Features ...............................................................................................................................................1
Features ......................................................................................................................................................................1
Other Features ............................................................................................................................................................1
Description ..................................................................................................................................................................1
Signal Information .......................................................................................................................................................6
Application Information ..............................................................................................................................................11
Crystal Selection Considerations ..............................................................................................................................12
1394 Application Support Contact Information ..........................................................................................................13
Absolute Maximum Ratings .......................................................................................................................................14
Electrical Characteristics ...........................................................................................................................................15
Timing Characteristics ...............................................................................................................................................18
Timing Waveforms ....................................................................................................................................................19
Internal Register Configuration ..................................................................................................................................20
Outline Diagrams .......................................................................................................................................................25
Ordering Information .................................................................................................................................................25
Figures
Figure 1. Block Diagram ..............................................................................................................................................5
Figure 2. Pin Assignments ..........................................................................................................................................6
Figure 3. Typical External Component Connections .................................................................................................11
Figure 4. Typical Port Termination Network ..............................................................................................................12
Figure 5. Crystal Circuitry ..........................................................................................................................................13
Figure 6. Dn, CTLn, and LREQ Input Setup and Hold Times Waveforms ................................................................19
Figure 7. Dn, CTLn Output Delay Relative to SYSCLK Waveforms ......................................................................... 19
Tables
Tables 1. Signal Descriptions ......................................................................................................................................7
Tables 2. Absolute Maximum Ratings .......................................................................................................................14
Tables 3. Analog Characteristics ...............................................................................................................................15
Tables 4. Driver Characteristics ................................................................................................................................16
Tables 5. Device Characteristics ...............................................................................................................................17
Tables 6. Switching Characteristics ..........................................................................................................................18
Tables 7. Clock Characteristics ................................................................................................................................18
Tables 8. PHY Register Map for the Cable Environment .........................................................................................20
Tables 9. PHY Register Fields for the Cable Environment .......................................................................................20
Tables 10. PHY Register Page 0: Port Status Page ................................................................................................22
Tables 11. PHY Register Port Status Page Fields ...................................................................................................23
Tables 12. PHY Register Page 1: Vendor Identification Page ................................................................................24
Tables 13. PHY Register Vendor Identification Page Fields .................................................................................24
2 2
Load Capacitance ..............................................................................................................................................13
Adjustment to Crystal Loading ...........................................................................................................................13
Crystal/Board Layout ..........................................................................................................................................13
64-Pin TQFP ......................................................................................................................................................25
Table of Contents
List of Figures
List of Tables
Data Sheet, Rev. 3
Agere Systems Inc.
May 2004
Page
Page
Page