L-FW802B-DB LSI, L-FW802B-DB Datasheet - Page 20

• Manufacturer Part Number: L-FW802B-DB
• Manufacturer: LSI

Specifications of L-FW802B-DB

• Lead Free Status / RoHS Status: Compliant

FW802B Low-Power PHY IEEE 1394A-2000
Two-Cable Transceiver/Arbiter Device
Internal Register Configuration
The PHY register map is shown below in Table 8. (Refer to IEEE 1394a-2000, 5B.1 for more information).
Table 8. PHY Register Map for the Cable Environment
The meaning of the register fields within the PHY register map are defined by Table 9 below. Power reset values
not specified are resolved by the operation of the PHY state machines subsequent to a power reset.
Table 9. PHY Register Fields for the Cable Environment
20
20
Physical_ID
Gap_count
Address
Extended
0000
0001
0010
0100
0101
1000
0011
0110
0111
1111
Field
RHB
IBR
PS
R
2
2
2
2
2
2
2
2
2
2
XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX
Watchdog
Size Type
6
1
1
1
1
6
3
RHB
LCtrl
Bit 0
rw
rw
rw
r
r
r
r
Extended (7)
Page_select
Max_speed
REQUIRED
Contender
Power Reset
ISBR
Bit 1
IBR
000000
Value
3F
—
0
0
0
7
16
Loop
Bit 2
Physical_ID
The address of this node determined during self-identification. A
value of 63 indicates a malconfigured bus; the link will not transmit
any packets.
When set to one, indicates that this node is the root.
Cable power active.
Root Hold-off Bit. When set to one, the force_root variable is
TRUE, which instructs the PHY to attempt to become the root dur-
ing the next tree identify process.
Initiate Bus Reset. When set to one, instructs the PHY to set ibr
TRUE and reset_time to RESET_TIME. These values in turn
cause the PHY to initiate a bus reset without arbitration; the reset
signal is asserted for 166 µs. This bit is self-clearing.
Used to configure the arbitration timer setting in order to optimize
gap times according to the topology of the bus. See Section 4.3.6
of IEEE Standard 1394a-2000 for the encoding of this field.
This field has a constant value of seven, which indicates the
extended PHY register map.
XXXXX
XXXXX
XXXXX
XXXXX
Pwr_fail
Register 0
Register 7
Jitter
Bit 3
Contents
RESERVED
Page_select
Page_select
Timeout
Bit 4
Gap_count
Description
Port_event Enab_accel Enab_multi
Bit 5
Port_select
Total_ports
Delay
Pwr_class
Data Sheet, Rev. 3
Bit 6
R
Agere Systems Inc.
May 2004
Bit 7
PS