L-FW802B-DB LSI, L-FW802B-DB Datasheet - Page 21

• Manufacturer Part Number: L-FW802B-DB
• Manufacturer: LSI

Specifications of L-FW802B-DB

• Lead Free Status / RoHS Status: Compliant

Data Sheet, Rev. 3
May 2004
Internal Register Configuration
Table 9. PHY Register Fields for the Cable Environment (continued)
Agere Systems Inc.
Max_speed
Total_ports
Port_event
Contender
Pwr_class
Watchdog
Pwr_fail
Timeout
Delay
Field
ISBR
LCtrl
Jitter
Loop
Size Type Power Reset Value
4
3
4
1
1
3
3
1
1
1
1
1
1
rw
rw
rw
rw
rw
rw
rw
rw
rw
r
r
r
r
See description.
See description.
0000
010
000
2
1
0
0
0
1
0
0
2
(continued)
The number of ports implemented by this PHY. This count
reflects the number.
Indicates the speed(s) this PHY supports:
000
001
010
011
100
101
All other values are reserved for future definition.
Worst-case repeater delay, expressed as 144 + (delay * 20) ns.
Link Active. Cleared or set by software to control the value of
the L bit transmitted in the node’s self-ID packet 0, which will be
the logical AND of this bit and LPS active.
Cleared or set by software to control the value of the C bit
transmitted in the self-ID packet. Powerup reset value is set by
C/LKON pin.
The difference between the fastest and slowest repeater data
delay, expressed as (jitter + 1) * 20 ns.
Power-Class. Controls the value of the pwr field transmitted in
the self-ID packet. See Section 4.3.4.1 of IEEE Standard
1394a-2000 for the encoding of this field. PC0, PC1, and PC2
pins set up power reset value.
When set to one, the PHY will set Port_event to one if resume
operations commence for any port.
Initiate Short (Arbitrated) Bus Reset. A write of one to this bit
instructs the PHY to set ISBR true and reset_time to
SHORT_RESET_TIME. These values in turn cause the PHY to
arbitrate and issue a short bus reset. This bit is self-clearing.
Loop Detect. A write of one to this bit clears it to zero.
Cable Power Failure Detect. Set to one when the PS bit
changes from one to zero. A write of one to this bit clears it to
zero.
Arbitration State Machine Timeout. A write of one to this bit
clears it to zero (see MAX_ARB_STATE_TIME).
Port Event Detect. The PHY sets this bit to one if any of con-
nected, bias, disabled, or fault change for a port whose
Int_enable bit is one. The PHY also sets this bit to one if
resume operations commence for any port and Watchdog is
one. A write of one to this bit clears it to zero.
2
2
2
2
2
2
= 98.304, 196.608, 393.216, and 786.43 Mbits/s
= 98.304 Mbits/s
= 98.304 and 196.608 Mbits/s
= 98.304, 196.608, and 393.216 Mbits/s
= 98.304, 196.608, 393.216, 786.432, and
= 98.304, 196.608, 393.216, 786.432, 1,572.864, and
1,572.864 Mbits/s
3,145.728 Mbits/s
FW802B Low-Power PHY IEEE 1394A-2000
Two-Cable Transceiver/Arbiter Device
Description
21