L-FW802B-DB LSI, L-FW802B-DB Datasheet - Page 4

• Manufacturer Part Number: L-FW802B-DB
• Manufacturer: LSI

Specifications of L-FW802B-DB

• Lead Free Status / RoHS Status: Compliant

Two-Cable Transceiver/Arbiter Device
Description
The FW802B supports suspend/resume as defined in
the IEEE 1394a-2000 specification. The suspend
mechanism allows an FW802B port to be put into a
suspended state. In this state, a port is unable to
transmit or receive data packets, however, it remains
capable of detecting connection status changes and
detecting incoming TPBias. When all ports of the
FW802B are suspended, all circuits except the bias
voltage reference generator and bias detection circuits
are powered down, resulting in significant power
savings. The use of suspend/resume is recommended.
Four signals are used as inputs to set four
configuration status bits in the self-identification (self-
ID) packet. These signals are hardwired high or low as
a function of the equipment design. PC[0:2] are the
three signals that indicate either the need for power
from the cable or the ability to supply power to the
cable. The fourth signal, C/LKON, as an input,
indicates whether a node is a contender for bus
manager. When the C/LKON signal is asserted, it
means the node is a contender for bus manager. When
the signal is not asserted, it means that the node is not
a contender. The C bit corresponds to bit 20 in the self-
ID packet. PC[0:2] corresponds to the pwr field of the
Self-ID packet in the following manner: PC0
corresponds to bit 21, PC1 corresponds to bit 22, and
PC2 corresponds to bit 23 (see Self-ID packets table in
section 4.3.4.1 of the IEEE 1394a-2000 standard for
additional details).
A powerdown signal (PD) is provided to allow a
powerdown mode where most of the PHY circuits are
powered down to conserve energy in battery-powered
applications. The internal logic in FW802B is reset as
long as the powerdown signal is asserted. A cable
status signal, CNA, provides a high output when none
of the twisted-pair cable ports are receiving incoming
bias voltage. This output is not debounced. The CNA
output can be used to determine when to power the
PHY down or up. In the powerdown mode, all circuitry
is disabled except the CNA circuitry. It should be noted
that when the device is powered down, it does not act
in a repeater mode.
When the power supply of the PHY is removed while
the twisted-pair cables are connected, the PHY
transmitter and receiver circuitry has been designed to
present a high impedance to the cable in order to not
load the TPBIAS signal voltage on the other end of the
cable.
Whenever the TBA±/TPB± signals are wired to a
connector, they must be terminated using the normal
termination network (See Figure 4). This is required for
reliable operation. For those applications, when one of
4
(continued)
the FW802B’s ports is not wired to a connector, those
unused to a connector, those unused ports may be left
unconnected without normal termination. When a port
does not have a cable connected, internal connect-
detect circuitry will keep the port in a disconnected
state.
Note: All gap counts on all nodes of a 1394 bus must
The link power status (LPS) signal works with the
C/LKON signal to manage the LLC power usage of the
node. The LPS signal indicates that the LLC of the
node is powered up or powered down. If LPS is inac-
tive for more than 1.2 µs and less than 25 µs, the
PHY/link interface is reset. If LPS is inactive for greater
than 25 µs, the PHY will disable the PHY/link interface
to save power. FW802B continues its repeater function
even when the PHY/link interface is disabled. If the
PHY then receives a link-on packet, the C/LKON sig-
nal is activated to output a 6.114 MHz signal, which
can be used by the LLC to power itself up. Once the
LLC is powered up, the LPS signal communicates this
to the PHY and the PHY/link interface is enabled. The
C/LKON signal is turned off when LPS is active or
when a bus reset occurs, provided the interrupt that
caused C/LKON is not present.
When the PHY/link interface is in the disabled state, the
FW802B will automatically enter a low-power mode, if
all ports are inactive (disconnected, disabled, or sus-
pended). In this low-power mode, the FW802B disables
its PLL and also disables parts of its reference circuitry
depending on the state of the ports (some reference cir-
cuitry must remain active in order to detect incoming TP
bias). The lowest power consumption (the microlow-
power sleep mode) is attained when all ports
are either disconnected or disabled with the ports inter-
rupt enable bit (see Table 11) cleared. The FW802B will
exit the low-power mode when the LPS input is
asserted high or when a port event occurs that requires
the FW802B to become active in order to respond to the
event or to notify the LLC of the event (e.g., incoming
bias or disconnection is detected on a suspended port,
a new connection is detected on a nondisabled port,
etc.). When the FW802B is in the low-power mode, the
SYSCLK output will become active (and the PHY/link
interface will be initialized and become operative) within
3 ms after LPS is asserted high.
Two of the FW802B’s signals are used to set up
various test conditions used only during the device
manufacturing process. These signals (SE and SM)
should be connected to V
be identical. The software accomplishes this by
issuing PHY configuration packets (see Section
4.3.4.3 of the IEEE 1394a-2000 standard) or by
issuing two bus resets, which resets the gap
counts to the maximum level (3Fh).
SS
for normal operation.
Agere Systems Inc.
May 2004