L-FW802B-DB LSI, L-FW802B-DB Datasheet - Page 23

• Manufacturer Part Number: L-FW802B-DB
• Manufacturer: LSI

Specifications of L-FW802B-DB

• Lead Free Status / RoHS Status: Compliant

Data Sheet, Rev. 3
May 2004
Internal Register Configuration
The meaning of the register fields with the port status page are defined by Table 11 below.
Table 11. PHY Register Port Status Page Fields
Agere Systems Inc.
Negotiated_speed
Connected
Int_enable
Disabled
Field
AStat
BStat
Child
Fault
Bias
Size Type
2
2
1
1
1
1
3
1
1
rw
rw
rw
r
r
r
r
r
r
Power Reset
Value
000
—
—
0
0
0
0
0
0
(continued)
TPA line state for the port:
00
01
10
11
TPB line state for the port (same encoding as AStat).
If equal to one, the port is a child; otherwise, a parent. The
meaning of this bit is undefined from the time a bus reset is
detected until the PHY transitions to state T1: Child Hand-
shake during the tree identify process (see Section 4.4.2.2 in
IEEE Standard 1394-1995).
If equal to one, the port is connected.
If equal to one, incoming TPBIAS is detected.
If equal to one, the port is disabled.
Indicates the maximum speed negotiated between this PHY
port and its immediately connected port; the encoding is the
same as for the PHY register Max_speed field.
Enable Port Event Interrupts. When set to one, the PHY
will set Port_event to one if any of connected, bias, disabled,
or fault (for this port) change state.
Set to one if an error is detected during a suspend or resume
operation. A write of one to this bit clears it to zero.
2
2
2
2
= Z
= invalid
= 1
= 0
FW802B Low-Power PHY IEEE 1394A-2000
Two-Cable Transceiver/Arbiter Device
Description
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