GDLXT9785MBC.D0-854707 Cortina Systems Inc, GDLXT9785MBC.D0-854707 Datasheet - Page 126

• Manufacturer Part Number: GDLXT9785MBC.D0-854707
• Manufacturer: Cortina Systems Inc

Specifications of GDLXT9785MBC.D0-854707

• Lead Free Status / RoHS Status: Not Compliant

LXT9785/LXT9785E
Datasheet
249241, Revision 11.0
16 April 2007
4.5.5
Table 42
4.6
4.6.1
4.6.1.1
4.6.1.2
Cortina Systems
Hardware Configuration Settings
The LXT9785/LXT9785E provides a hardware option to set the initial device configuration.
The hardware option uses three Global CFG pins that provide control for all ports (see
Table
Global Hardware Configuration Settings
Link Establishment
Auto-Negotiation
The LXT9785/LXT9785E attempts to auto-negotiate with its link partner by sending Fast
Link Pulse (FLP) bursts. Each burst consists of 33 link pulses spaced 62.5 μs apart. Odd
link pulses (clock pulses) are always present. Even link pulses (data pulses) may also be
present or absent to indicate a “1” or a “0”. Each FLP burst exchanges 16 bits of data,
referred to as a “page”. All devices that support auto-negotiation must implement the
“Base Page”, defined by IEEE 802.3 (registers 4 and 5). The LXT9785/LXT9785E also
supports the optional “Next Page” function (registers 7 and 8).
Base Page Exchange
By exchanging Base Pages, the LXT9785/LXT9785E and its link partner communicate
their capabilities to each other. Both sides must receive at least three identical base pages
for negotiation to proceed. Each side finds their highest common capabilities, exchange
more pages, and agree on the operating state of the line.
Manual Next Page Exchange
Additional information, exceeding that required by base page exchange, is also sent via
“Next Pages.” The LXT9785/LXT9785E fully supports the IEEE 802.3 method of
negotiation via Next Page exchange. The Next Page exchange uses Register 7 to send
information and Register 8 to receive it. Next Page exchange occurs only if both ends of
the link partners advertise their ability to exchange Next Pages. A special mode has been
added to make manual next page exchange easier for software. When Register 6 “page”
®
1. Refer to
AutoNeg
Disabled
Enabled
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Considerations, on page 50 Table 24, RMII Signal Descriptions – BGA23, on page 80
Receive FIFO Depth Configurations, on page
for CFG pin assignments.
42).
Desired Mode
Table 5, RMII Signal Descriptions – PQFP, on page 36
Speed
10/100
100
100
10
Full/Half
Full/Half
Duplex
Half
Half
Half
Half
Full
Full
High
High
High
High
High
High
Low
Low
1
Pin Settings
CFG
High
High
High
High
Low
Low
Low
Low
2
96, and
High
High
High
High
1
Low
Low
Low
Low
3
Table 39, BGA15 Signal Descriptions, on page 106
0.12
0
1
0.13
through
Resulting Register Bit Values
0
1
1
1
1
1
Table 17, Receive FIFO Depth
0.8
0
1
0
1
0
0
0
0
4.8
4.6 Link Establishment
0
1
0
1
Auto-Negotiation
Advertisement
through
4.7
1
1
1
1
N/A
4.6
Table 36,
0
0
1
Page 126
4.5
0
1
1