GDLXT9785MBC.D0-854707 Cortina Systems Inc, GDLXT9785MBC.D0-854707 Datasheet - Page 186

• Manufacturer Part Number: GDLXT9785MBC.D0-854707
• Manufacturer: Cortina Systems Inc

Specifications of GDLXT9785MBC.D0-854707

• Lead Free Status / RoHS Status: Not Compliant

LXT9785/LXT9785E
Datasheet
249241, Revision 11.0
16 April 2007
Table 76
Figure 55
Table 77
Cortina Systems
RMII - 100BASE-FX Transmit Timing Parameters
RMII - 10BASE-T Receive Timing
RMII - 10BASE-T Receive Timing Parameters
®
TxData<1:0>/TxEN setup to REFCLK rising edge
TxData<1:0>/TX-EN hold from REFCLK rising
edge
TxEN sampled to TPFO out (Tx latency)
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
2. “BT” signifies bit times at the line rate (that is, BT = 100 ns if using 10BASE-T, BT = 10 ns if using
Note:
RxData<1:0>, CRS_DV setup to REFCLK rising
edge
RxData<1:0>, CRS_DV hold from REFCLK rising
edge
TPFI in to CRS_DV asserted
TPFI quiet to CRS_DV de-asserted
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
2. “BT” signifies bit times at the line rate (that is, BT = 100 ns if using 10BASE-T, BT = 10 ns if using
3. Values and conditions from RMII Specification, Rev. 1.2.
Note:
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
RxData[1:0]
testing.
100BASE-TX or 100BASE-FX).
testing.
100BASE-TX or 100BASE-FX).
3
3
CRS_DV
REFCLK
The table latency values are derived with the hardware configuration pins FIFOSEL[1:0] set at a
default configuration of 00 (32 bits of initial fill).
The table latency values are derived with the hardware configuration pins FIFOSEL[1:0] set at a
default configuration of 00 (32 bits of initial fill).
TPFI
Parameter
Parameter
t
3
Sym
Sym
t1
t2
t3
t4
t1
t2
t3
t
1
Min
1.5
Min
12
4
2
4
2
–
t
2
Typ1
Typ1
15
–
–
3
10
–
–
t
4
Max
Max
14
14
16
4
12
–
–
6.0 Test Specifications
Units
BT
BT
Units
ns
ns
BT
ns
ns
2
2
2
Conditions
Conditions
Test
Test
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