GDLXT9785MBC.D0-854707 Cortina Systems Inc, GDLXT9785MBC.D0-854707 Datasheet - Page 149

• Manufacturer Part Number: GDLXT9785MBC.D0-854707
• Manufacturer: Cortina Systems Inc

Specifications of GDLXT9785MBC.D0-854707

• Lead Free Status / RoHS Status: Not Compliant

LXT9785/LXT9785E
Datasheet
249241, Revision 11.0
16 April 2007
4.11.3
Cortina Systems
Management Interface and Control
The management and control of the DTE discovery process is via the MDIO port. Each
port on the LXT9785E is capable of running the discovery process, thus each port is
independently controlled. This is achieved by each port having a dedicated set of control
and status bits. These bits are found in Register 27 as follows:
DTE DISCOVERY PROCESS ENABLE - Register Bit 27.6 (Dis_EN)
R/W Default value = 0: Disabled.
Register bit 27.6 controls the operation of the process. The discovery process is disabled
when Register bit 27.6 = 0, and enabled when Register bit 27.6 = 1. The MAC controller
sets Register bit 27.6 to a 1 when a port search for a DTE requiring power is desired.
Once set, Register bit 27.6 remains = 1 until the MAC clears it, either by directly clearing it
or by resetting the PHY. This allows the discovery process to continue to function if
unsuccessful in detecting a DTE, without being continually re-enabled by the MAC. If
Register bit 27.6 is set after link is established, no action is taken until after the link goes
down.
POWER ENABLE - Register Bit 27.4 (Power_EN)
R Default value = 0: No Remote-Power DTE found.
Register bit 27.4 contains the result of the discovery process. When Register bit 27.4 = 0,
the discovery process has not found Remote-Power DTE, and when Register bit 27.4 = 1,
the discovery process has potentially found a DTE requiring power. This indicates power
should be applied to the Category 5 cable. Register bit 27.4 is polled by the MAC during
the discovery process, and is cleared when the PHY is reset, when auto-negotiation is
restarted, or when auto-negotiation is disabled. In the event of a discovery process being
interrupted due to detection of an already powered link partner (auto-negotiation
completion or Parallel Detection), Register bit 27.4 = 0.
STANDARD LINK PARTNER DETECTED - Register Bit 27.3 (SLP_Det)
R/W Clear on Read Default value = 0: No link partner found.
When Register bit 27.3 = 1, a standard link partner has been detected by the LXT9785E
(NLPs, MLT3 data, FLPs without next page support, or FLPs with non-matching next
pages). This indicates power should not be applied to the Category 5 cable. When
Register bit 27.3 = 0, other bits are checked to determine overall status of the link partner.
Register bit 27.3 is cleared on read, or DTE discovery is disabled, link is established, or
auto-negotiation is either restarted or disabled.
LINK FAIL TIMEOUT - Register Bit 27.2 (LFIT Expired)
R/W Clear on Read Default value = 0 (Link Fail Inhibit timer has expired without
establishment of link with a standard link partner). Valid only when Standard Link Partner
Detected Register bit 27.3 = 1.
®
5. If power is applied and link is established, the system must still poll the Link Status
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
negotiation mode was used to establish link with the phone, and the DTE process is
still enabled. The LXT9785E restarts negotiation without DTE detection if either forced
speed mode is used to establish link with the phone, or the DTE process is disabled.
Register bit 1.2 for the corresponding LXT9785E port or the link status change
interrupt. This is required since link status is the only way to know when the Remote-
Power DTE is removed or unplugged. On seeing the Link_Down condition, the
processor instructs the power supply to switch off, and the DTE Discovery begins
again or is disabled.
4.11 DTE Discovery Process
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