GDLXT9785MBC.D0-854707 Cortina Systems Inc, GDLXT9785MBC.D0-854707 Datasheet - Page 200

• Manufacturer Part Number: GDLXT9785MBC.D0-854707
• Manufacturer: Cortina Systems Inc

Specifications of GDLXT9785MBC.D0-854707

• Lead Free Status / RoHS Status: Not Compliant

LXT9785/LXT9785E
Datasheet
249241, Revision 11.0
16 April 2007
Table 93
Table 94
Cortina Systems
Port Configuration Register (Address 16, Hex 10)
Quick Status Register (Address 17, Hex 11)
®
1. R/W = Read/Write
2. LSHR = Default value is derived from a single device input pin state or a group of device input pin states as
3. The default value of Register bit 16.0 is determined by the G_FX/TP_L pin.
4. The default value of Register bit 16.5 is determined by the PREASEL pin. The BGA15 package does not
5. The BGA15 package does not support fiber. Default for the BGA15 package is 0.
6. NA means the bits do not have a default value and may initially contain any value.
1. R = Read Only, LH = Latching High – cleared when read.
2. The default values are updated on completion of reset and reflect the status or change in status at that
3. The default value is determined by the default value of Register bit 0.12.
4. LSHR = Default value is derived from a single device input pin state or a group of device input pin states as
5. Default values are set by the hardware configuration PAUSE pin. The BGA15 package does not have a
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Bit
Bit
15
14
13
12
11
10
9
8
1
0
the pin(s) are latched at startup or hardware reset.
If G_FX/TP_L is tied Low, the default value of Register bit 16.0 = 0. If G_FX/TP_L is not tied Low, the
default value of Register bit 16.0 = 1. The BGA15 package does not have a G_FX/TP_L hardware
configuration pin.
have a PREASEL hardware configuration pin and has a default of 0.
time. Cortina recommends that the register status be read on completion of reset.
the pin(s) are latched at startup or hardware reset.
Pause hardware configuration pin. The default for the BGA15 package is 0.
Name
Reserved
10/100 Mode
Transmit Status
Receive Status
Collision Status
Link
Duplex Mode
Auto-Negotiation
Name
Reserved
Fiber Select
Reserved for
BGA15
5
Description
Write as 0, ignore on Read
0 = The LXT9785/LXT9785E is operating in 10 Mbps
1 = The LXT9785/LXT9785E is operating in 100 Mbps
Note:
0 = The LXT9785/LXT9785E is not transmitting a packet
1 = The LXT9785/LXT9785E is transmitting a packet
0 = Packet has not been received since last read
1 = Packet has been received since last read
0 = A collision is not occurring
1 = A collision is occurring
Note:
0 = Link is down
1 = Link is up
0 = Half-duplex
1 = Full-duplex
0 = The LXT9785/LXT9785E is in manual mode
1 = The LXT9785/LXT9785E is in auto-negotiation mode
This signal is based upon Register bit 0.12.
Description
Write as 0, ignore on Read.
0 = Select twisted-pair mode for this port
1 = Select fiber mode for this port
Write as '0', ignore on Read (BGA15).
Note:
mode
mode
The status is valid for TX and FX operation.
This bit is set when jabber is detected, regardless
of duplex. Status is valid only when link is up.
Default for BGA15 is 0.
7.0 Register Definitions
Type
Type
R/W
R/W
LH
LH
LH
R
R
R
R
R
R
R
R
1
1
Page 200
LSHR
Default
Default
Note 3
0
0
0
0
0
0
0
0
2
2,3