ICS1892YT IDT, Integrated Device Technology Inc, ICS1892YT Datasheet - Page 87

• Manufacturer Part Number: ICS1892YT
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of ICS1892YT

• Lead Free Status / RoHS Status: Not Compliant

8.11.1 Command Override Write Enable (bit 16.15)
8.11.2 ICS Reserved (bits 16.14:11)
8.11.3 PHY Address (bits 16.10:6)
8.11.4 Stream Cipher Scrambler Test Mode (bit 16.5)
8.11.5 ICS Reserved (bit 16.4)
8.11.6 NRZ/NRZI Encoding (bit 16.3)
ICS1892, Rev. D, 2/26/01
The Command Override Write Enable bit provides an STA the ability to alter the Command Override Write
(CW) bits located throughout the MII Register set. A two-step process is required to alter the value of a CW
bit:
1. Step one is to issue a Command Override, that is, bit 16.15 is set to logic one.
2. Step two immediately follows, which is a write to the CW bit that you wish to change. (The Command
ICS is reserving these bits for future use. Functionally, these bits are equivalent to IEEE Reserved bits.
When one of these reserved bits is:
•
•
ICS uses some of these reserved bits to invoke auxiliary functions. To ensure proper operation of the
ICS1892, an STA must maintain the default value of these bits. Therefore, ICS recommends that an STA
always write the default value of any reserved bits during all management register write operations.
These five bits hold the Serial Management Port Address of the ICS1892. During either a hardware reset
or a power-on reset, the PHY address is read from the LED interface. (For information on the LED
interface, see
Address and LED
Address bits is unaffected by a software reset.)
The Stream Cipher Scrambler Test Mode bit is used to force the ICS1892 to lose LOCK, thereby requiring
the Stream Cipher Scrambler to resynchronize.
See
This bit allows an STA to control whether NRZ (Not Return to Zero) or NRZI (Not Return to Zero, Invert on
One) encoding is applied to the serial transmit data stream in 100Base-TX mode. When this bit is logic:
•
•
Read by an STA, the ICS1892 returns a logic zero.
Written to by an STA, the STA must use the default value specified in this data sheet.
Zero, the ICS1892 encodes the serial transmit data stream using NRZ encoding.
One, the ICS1892 encodes the serial transmit data stream using NRZI encoding.
ICS1892
Override Write Enable bit is a Self-Clearing bit that is automatically reset to logic zero after the next MII
write, thereby allowing only one subsequent write to alter a CW bit.)
Section 8.11.2, “ICS Reserved (bits
Section 6.9, “Status Interface”
Pins”). The PHY address is then latched into this register. (The value of each of the PHY
© 2000-2001, Integrated Circuit Systems, Inc.
All rights reserved.
16.14:11)”, the text for which also applies here.
and
87
Section 9.2.2, “Multi-Function (Multiplexed) Pins: PHY
Chapter 8 Management Register Set
February 26, 2001