FWLXT9784BE.A3 Cortina Systems Inc, FWLXT9784BE.A3 Datasheet - Page 25

• Manufacturer Part Number: FWLXT9784BE.A3
• Manufacturer: Cortina Systems Inc

Specifications of FWLXT9784BE.A3

• Lead Free Status / RoHS Status: Not Compliant

Datasheet
Table 7. Miscellaneous Signal Descriptions
Y11, A11
Y10, A10
K3
K18
J1, K2, L2
L20, L19
B18
K19
K20
K1
L3
G18
H19
H18
H20
B20
1. Refer to
Ball ID
Table 1 on page 11
Signal Name
RBIAS10_0
RBIAS10_1
RBIAS100_0
RBIAS100_1
MCLK
RESET
MODE_0
MODE_1
MODE_2
ID_0
ID_1
INT
BP4B5B
SCRMBP
FRCLNK
FRC34
MDI-X
TI
TEXEC
TCK
TOUT
Type
I-PD
I-PD
I-PD
I-PD
I-PD
I-PU
OD
O
B
B
I
I
I
I
I
I
for Signal Type Definitions.
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Bias Reference Resistor 10. A 464
from this pin to ground. This determines the current source in 10M mode.
Bias Reference Resistor 100. A 619
from this pin to ground. This determines the current source in 100M
mode.
Master Clock. The LXT9784 master input clock, 35/65 duty cycle,
The MCLK frequency varies, based on the mode. Mode is set by the
MODE<2:0> pins.
In RMII mode, MODE<2:0> = 001, MCLK = 50 MHz
In SMII mode, MODE<2:0> = 010, MCLK = 125 MHz
Reset. The Reset signal is active high and resets the LXT9784. A reset
pulse width of at least 500 s should be used.
Mode of Operation. Sets the LXT9784 mode of operation. See Table 10.
ID. Sets the two most significant bits of the PHY addresses.
The ID<1:0> pins are used to set the PHY addresses for accessing the
PHY registers through the MII management interface.
Link Status Interrupt. The Link status change interrupt line.
4B5B encoder Bypass. If BP4B5B is high, the 4B5B encoder / 5B4B
decoder will be bypassed in 100 Mbps mode of operation.
Scrambler/Descrambler Bypass. If SCRMBP is high, the scrambler/
descrambler of TP-PMD will be bypassed in 100 Mbps mode of
operation.
Force Link. When high, force good link at speed of operation.
Force 34 Pattern. When high, force the 34 pattern in 100M only.
MDI-X Enable. When high, enable the MDI/MDI-X automatic detection
and switch-over feature.
Test Input. Sets the device into manufacturing test mode
(MODE<2:0>=”111”). Should be externally pulled low when not in use.
Test Execute Command. Sets the device into async test mode
(MODE<2:0>=”111”). Should be externally pulled low when not in use.
Test Clock. The test clock signal. Should be externally pulled low when
not in use.
Test Output. The test output port.
50ppm.
Low-Power Octal PHY — LXT9784
Description
resistor should be connected
resistor should be connected
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