FWLXT9784BE.A3 Cortina Systems Inc, FWLXT9784BE.A3 Datasheet - Page 33

• Manufacturer Part Number: FWLXT9784BE.A3
• Manufacturer: Cortina Systems Inc

Specifications of FWLXT9784BE.A3

• Lead Free Status / RoHS Status: Not Compliant

2.3.2
2.3.2.1
2.3.2.2
Datasheet
Figure 7. SMII Received Serial Data Stream
RXD_n
MCLK
SYNC
100BASE-TX Transmitter
The transmit subsection of the LXT9784 PHY device accepts di-bit data on TXDn_[1:0] (RMII
interface) or serial stream data on TXDn (SMII interface) while TXENn is asserted (High). The
data is assembled into nibbles and passed to the 4B/5B encoder as long as TXENn is active.
The 4B/5B encoder compiles the data into 5-bit-wide parallel symbols. These symbols are
scrambled and serialized into a 125 Mbps bit stream, converted by the analog transmit driver into
an MLT-3 waveform format, and transmitted onto the unshielded twisted pair (UTP) or Type 1
shielded twisted pair (STP) wire.
100BASE-TX 4B/5B Encoder
The 4B/5B encoder complies with the IEEE 802.3u 100BASE-TX standard. Four bits at a time are
accepted and encoded according to the TX 4B/5B look-up table. The lookup table matches a 5-bit
code to each 4-bit code. Refer to Table 12.
100BASE-TX Scrambler and MLT-3 Encoder
Data is scrambled in 100BASE-TX to reduce electromagnetic emissions during long transmissions
of high-frequency data codes. The scrambler logic accepts 5 bits from the 4B/5B encoder block,
then presents scrambled data to the MLT-3 encoder. The LXT9784 PHYs implement the 11-bit
Stream Cipher scrambler as adopted by the ANSI XT3T9.5 committee for unshielded twisted-pair
operation. The cipher equation used is: X[n] = X[n-11] + X[n-9] (mod 2).
The encoder receives the scrambled NRZ data stream from the scrambler and encodes the stream
into MLT-3 for presentation to the driver. MLT3 is similar to NRZI coding, but three levels are
output instead of two. There are three output levels +, 0 and -. When an NRZ “0” arrives at the
input of the encoder, the last output level is maintained unchanged (either +, 0 or -) When an NRZ
“1” arrives at the input of the encoder, the output steps to the next level. The order of steps is “-
,0,+,0,-,0...” See
CRS
RX_DV
Figure
RXD0
8.
Receive stream direction
RXD1
RXD2
RXD3
RXD4
Low-Power Octal PHY — LXT9784
RXD5
RXD6
RXD7
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