FWLXT9784BE.A3 Cortina Systems Inc, FWLXT9784BE.A3 Datasheet - Page 43

• Manufacturer Part Number: FWLXT9784BE.A3
• Manufacturer: Cortina Systems Inc

Specifications of FWLXT9784BE.A3

• Lead Free Status / RoHS Status: Not Compliant

2.11
Datasheet
Table 17. LED Functionality
Table 18. Activity LED Blink Rates
Table 19. MII Management Frame Format
During reset, all LED drivers are active for approximately 2 seconds, then turned off.
MII Management Interface Operation
The LXT9784 provides PHY status and accepts PHY management information via the MII
management interface. This is accomplished via read and write operations to various registers
according to the IEEE802.3u Standard. A read or write of a particular register is called a
management frame, which is sent serially over the MDIO pin synchronous to MDC at a maximum
rate of 3 MHz. Read and write cycles are from the perspective of the controller. Therefore, the
controller would always drive the Start, Opcode, PHY Address and Register Address on to the
MDIO pin. For a write, the controller would also drive the transition bits and data. For a read, the
LXT9784 drives the transition bits and data onto the MDIO pin. The controller should drive
address and data on the falling edge of MDC and the LXT9784 latches that data on the rising edge
of MDC. The PHY addresses in the LXT9784 can be configured from 0-31. The management
frame structure is shown in
This structure allows a controller or other management hardware, to query a PHY for status of the
link, auto-negotiation registers, or configure the PHY to one of many modes.
protocol terms.
When MDIO and MDC are not in use, they should be connected to pull-up devices.
LEDn_A
LEDn_B
LEDn_C
Percent Utilization
LED driver
1. n indicates Port Number.
1. Note: Duty Cycle = 50%
Function
WRITE
READ
5-30%
+30%
0-5%
Preamble
link solid /activity blink
speed
collision
1...1
1...1
Function
Blink Rate
medium
Frame
slow
Start
fast
Table
10
01
1
19.
Opcode
10
01
With a good link the output is low, the output toggles at a rate
related to the utilization.
Refer to
The output is low for 100 Mbps, high for 10 Mbps
The output blinks low with collisions stretch rate of 10 ms.
Frequency
PHY Adr
3 Hz
5 Hz
7 Hz
AAAAA
AAAAA
Table 18
for the actual numbers.
Reg adr
RRRRR
RRRRR
Low-Power Octal PHY — LXT9784
Description
Turnaround
Z0
10
Table 20
D[15:0]
D[15:0]
Data
defines the
Idle
Z
Z
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