FWLXT9784BE.A3 Cortina Systems Inc, FWLXT9784BE.A3 Datasheet - Page 50

• Manufacturer Part Number: FWLXT9784BE.A3
• Manufacturer: Cortina Systems Inc

Specifications of FWLXT9784BE.A3

• Lead Free Status / RoHS Status: Not Compliant

LXT9784 — Low-Power Octal PHY
3.4.1
50
Figure 14. Typical SMII Application
Data and control bits are transmitted and received serially synchronous to MCLK, in ten bit
segments delimited by a pulse on SYNC, on RXDn and TXDn respectively.
SMII Clock
In SMII mode of operation, the master input clock (MCLK) frequency should be 125 MHz, ±
50ppm, with a duty-cycle between 35% and 65% inclusive.
LED0_[A:C]
LED1_[A:C]
LED2_[A:C]
LED3_[A:C]
LED4_[A:C]
LED5_[A:C]
LED6_[A:C]
LED7_[A:C]
RBIAS100_0
RBIAS100_1
RBIAS10_0
RBIAS10_1
P0_MDI
P1_MDI
P2_MDI
P3_MDI
P4_MDI
P5_MDI
P6_MDI
P7_MDI
TPOP
ID[1:0]
TPIP
TPIN
TPON
MDIO
MDC
INT
MII Management
Per Port
Analog pins
PHY ID
MDI Ports
Interrupt
LEDs
Interface
LXT9784
Configuration
Interfaces
Test Port
SMII
SMII0_[1:0]
SMII1_[1:0]
SMII2_[1:0]
SMII3_[1:0]
SMII4_[1:0]
SMII5_[1:0]
SMII6_[1:0]
SMII7_[1:0]
MODE[2:0]
SCRMBP
FRCLNK
BP4B5B
RESET
TEXEC
FRC34
TOUT
MCLK
SYNC
MDIX
TCK
TI
RXD
TXD
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