FWLXT9784BE.A3 Cortina Systems Inc, FWLXT9784BE.A3 Datasheet - Page 42

• Manufacturer Part Number: FWLXT9784BE.A3
• Manufacturer: Cortina Systems Inc

Specifications of FWLXT9784BE.A3

• Lead Free Status / RoHS Status: Not Compliant

LXT9784 — Low-Power Octal PHY
2.9
2.10
42
Figure 11. Simplified Interrupt Structure
Port Interrupt Enable from register 12’h
Port Interrupt Enable from register 12’h
Port Interrupt Enable from register 12’h
Port 0 Status Changed = 1
Port 7 Status Changed = 1
Reset
When the LXT9784 RESET signal is asserted (active high) all internal circuits are reset. The PHY
can also be reset individually via the PHY register reset bit (register 0 ’h bit 15). Device clock
should be stable and running prior to HW RESET. Reset must be asserted for a minimum of 500 s
for proper operation after de-assertion.
LED Operation
The LXT9784 has three pins per port dedicated to driving the LEDs. These drivers can indicate
link/activity, speed, and collision. The drivers also indicate that the PHY port was disabled by
management. The activity LED in this mode is triggered by both transmit and receive activities. All
three drivers are active Low.
The algorithm for computing media utilization is an average of the activity on the media over the
time of 8 maximum length packets, with minimum IPG spacing. The utilization is averaged over:
(8 packets * 1518 bytes * 8 bytes/bit * bit time) + (8 IPG * 96 bits * bit time)
The percent utilization is indicated by a specific frequency on the LEDn_A (as shown in Table 17)
for a period of 600 ms (LED refresh rate), based on the activity of the prior 600 ms period.
In case the port is disabled, register 0.10 = 1, drivers LEDn_A and LEDn_B blink in unison, at a
rate of 1 Hz, 500 ms on and 500 ms off. Eliminate the indication of PHY port disable by setting the
PHY register 1B’h, bit 4. There is full controllability on all drivers through PHY register 1B’h, bits
[2:0].
The LEDn_B state is frozen when a link is lost and is changed only after the link is re-established.
Port 1 Status Changed = 1
Phy register 12’ h bit 0
Phy register 12’ h bit 0
.
.
.
Read
Read
INT_L
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