HBLXT9785HC.A4 Intel, HBLXT9785HC.A4 Datasheet - Page 127

• Manufacturer Part Number: HBLXT9785HC.A4
• Manufacturer: Intel

Specifications of HBLXT9785HC.A4

• Lead Free Status / RoHS Status: Not Compliant

4.5.3.1
4.5.3.2
4.5.4
Datasheet
Document Number: 249241
Revision Number: 010
Revision Date: 30-May-2006
Note: Intel recommends that a minimum recovery time be allowed after bringing up a port from software
or hardware power-down or link hold-off modes. The recovery times are specified in
“Power-Up Timing Parameters” on page 198
Global (Hardware) Power Down
The global power-down mode is controlled by the PWRDWN pin. When PWRDWN is High, the
following conditions are true:
Port (Software) Power Down
Individual port power-down control is provided by Register bit 0.11 in the respective port Control
Registers (refer to
power-down, the following conditions are true:
Reset
The LXT9785/LXT9785E provides both hardware and software resets. Configuration control of
Auto-Negotiation, speed, and duplex mode selection is handled differently for each. During a
hardware reset, settings for bits 0.13, 0.12, 0.8, and 4.8:5 are read in from the pins (refer to
Table 42, “Global Hardware Configuration Settings” on page 128
“Control Register (Address 0)” on page 200
Register (Address 4)” on page 204
During a software reset (Register bit 0.15 = 1), the bit settings are not re-read from the pins and
revert back to the values that were read in during the last hardware reset. Any changes to pin values
from the last hardware reset are not detected during a software reset.
During a hardware reset, register information is unavailable for 1 ms after de-assertion of the reset.
All MII interface pins are disabled during a hardware reset and released to the bus on de-assertion
of reset.
During a software reset (0.15 = 1) the registers are available for reading. The reset bit should be
polled to see when the part has completed reset (0.15 = 0). Pull up and pull down resisters are not
affected.
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All LXT9785/LXT9785E ports and the clock are shut down.
All outputs are three-stated.
All weak pad pull-up and pull-down resistors are disabled.
The MDIO registers are not accessible.
Configuration pins are read upon release of the PWRDWN pin, and registers are loaded with
the current values of the hardware configuration pins.
The individual port is shut down.
The MDIO registers remain accessible.
Pull-up and pull-down resisters are not affected and the outputs are not three-stated.
The register remains unchanged.
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 83, “Control Register (Address 0)” on page
for register bit definitions).
and
Table 87, “Auto-Negotiation Advertisement
for pin settings, and
200). During individual port
Table 80,
Table 83,
127