HBLXT9785HC.A4 Intel, HBLXT9785HC.A4 Datasheet - Page 41

• Manufacturer Part Number: HBLXT9785HC.A4
• Manufacturer: Intel

Specifications of HBLXT9785HC.A4

• Lead Free Status / RoHS Status: Not Compliant

Datasheet
Document Number: 249241
Revision Number: 010
Revision Date: 30-May-2006
Table 10. Signal Detect – PQFP
Table 11. Network Interface Signal Descriptions – PQFP
1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS =
2. The IP/ID resistors are disabled during H/W Power-Down mode.
3. Tie SD[0:7] inputs to GNDPECL if unused.
1. Type Column Coding: AI = Analog Input, AO = Analog Output.
2. Switched to Inputs (see TPFIP/N description) when not in fiber mode and MDIX is not active [that is,
3. Switched to Outputs (see TPFOP/N description) when not in fiber mode and MDIX is not active [that is,
PQFP
107, 108
121, 122
125, 124
136, 137
140, 139
150, 151
154, 153
104, 105
129, 128
132, 133
143, 142
146, 147
157, 156
Pin/Ball Designation
111, 110
115, 114
118, 119
100
101
161
162
165
166
PQFP
95
96
97
Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pull-
Down.
twisted-pair, non-crossover MDI mode].
twisted-pair, non-crossover MDI mode].
Designation
Pin/Ball
PBGA
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
P15,
P16,
P17,
N17
P2,
N4,
P3,
N5,
P1
T10, R10,
U13, T12,
R12, T13,
T11, U11,
T14,U15,
R14, T15
R16, T16
T2, U1,
T3, R4,
T6, U5,
U7, T7,
R2, T1,
U3, T4,
R6, T5,
T8, R8,
T9, U9,
PBGA
SD_2P5V
Symbol
SD0
SD1
SD2
SD3
SD4
SD5
SD6
SD7
TPFOP0, TPFON0
TPFOP1, TPFON1
TPFOP2, TPFON2
TPFOP3, TPFON3
TPFOP4, TPFON4
TPFOP5, TPFON5
TPFOP6, TPFON6
TPFOP7, TPFON7
TPFIP0, TPFIN0
TPFIP1, TPFIN1
TPFIP2, TPFIN2
TPFIP3, TPFIN3
TPFIP4, TPFIN4
TPFIP5, TPFIN5
TPFIP6, TPFIN6
TPFIP7, TPFIN7
Symbol
I, ST, ID
Type
I
1
Signal Description
Signal Detect 2.5 Volt Interface.
SD input threshold voltage select.
Tie to VCCPECL = Select 2.5 V LVPECL input levels
Float or Tie to GNDPECL = Select 3.3 V LVPECL input
levels
Signal Detect - Ports 0-7.
Signal Detect input from the fiber transceiver (these inputs
are only active for ports operating in fiber mode).
Logic High = Normal operation (the process of searching
for receive idles for the purpose of bringing link up is
initiated)
Logic Low = Link is declared lost
Type
AO/AI
AI/AO
1
Signal Description
Twisted-Pair/Fiber Outputs
Negative, Ports 0-7.
During 100BASE-TX or 10BASE-T operation,
TPFO pins drive 802.3 compliant pulses onto
the line.
During 100BASE-FX operation, TPFO pins
produce differential LVPECL outputs for fiber
transceivers.
Twisted-Pair/Fiber Inputs
Negative, Ports 0-7.
During 100BASE-TX or 10BASE-T operation,
TPFI pins receive differential 100BASE-TX or
10BASE-T signals from the line.
During 100BASE-FX operation, TPFI pins
receive differential LVPECL inputs from fiber
transceivers.
2,3
3
, Positive &
2
, Positive &
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