HBLXT9785HC.A4 Intel, HBLXT9785HC.A4 Datasheet - Page 128

• Manufacturer Part Number: HBLXT9785HC.A4
• Manufacturer: Intel

Specifications of HBLXT9785HC.A4

• Lead Free Status / RoHS Status: Not Compliant

128
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
4.5.5
4.6
4.6.1
4.6.1.1
Table 42. Global Hardware Configuration Settings
Intel recommends that a minimum recovery time be allowed after bringing up a port from software
or hardware reset. The recovery times are specified in
page 198
Hardware Configuration Settings
The LXT9785/LXT9785E provides a hardware option to set the initial device configuration. The
hardware option uses three Global CFG pins that provide control for all ports (see
Link Establishment
Auto-Negotiation
The LXT9785/LXT9785E attempts to auto-negotiate with its link partner by sending Fast Link
Pulse (FLP) bursts. Each burst consists of 33 link pulses spaced 62.5 μs apart. Odd link pulses
(clock pulses) are always present. Even link pulses (data pulses) may also be present or absent to
indicate a “1” or a “0”. Each FLP burst exchanges 16 bits of data, referred to as a “page”. All
devices that support auto-negotiation must implement the “Base Page”, defined by IEEE 802.3
(registers 4 and 5). The LXT9785/LXT9785E also supports the optional “Next Page” function
(registers 7 and 8).
Base Page Exchange
By exchanging Base Pages, the LXT9785/LXT9785E and its link partner communicate their
capabilities to each other. Both sides must receive at least three identical base pages for negotiation
to proceed. Each side finds their highest common capabilities, exchange more pages, and agree on
the operating state of the line.
AutoNeg
Disabled
Enabled
1. Refer to
Considerations” on page 49 Table 24, “RMII Signal Descriptions – BGA23” on page 81
“Receive FIFO Depth Configurations” on page
Descriptions” on page 108
Desired Mode
Table 5, “RMII Signal Descriptions – PQFP” on page 35
Speed
10/100
100
100
10
Full/Half
Full/Half
Duplex
Half
Half
Half
Half
Full
Full
for CFG pin assignments.
High
High
High
High
High
High
Low
Low
1
Pin Settings
CFG
High
High
High
High
Low
Low
Low
Low
2
97, and
1
High
High
High
High
Low
Low
Low
Low
3
Table 39, “Intel® LXT9785 BGA15 Signal
Table 80, “Power-Up Timing Parameters” on
0.12
0
1
0.13
through
Resulting Register Bit Values
0
1
1
1
1
1
0.8
Table 17, “Receive FIFO Depth
0
1
0
1
0
0
0
0
4.8
0
1
0
1
Revision Date: 30-May-2006
Document Number: 249241
Auto-Negotiation
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through
4.7
Revision Number: 010
1
1
1
1
Table
N/A
Datasheet
4.6
Table 36,
0
0
1
42).
4.5
0
1
1