HBLXT9785HC.A4 Intel, HBLXT9785HC.A4 Datasheet - Page 185

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HBLXT9785HC.A4

Manufacturer Part Number
HBLXT9785HC.A4
Description
Manufacturer
Intel
Datasheet

Specifications of HBLXT9785HC.A4

Lead Free Status / RoHS Status
Not Compliant
Datasheet
Document Number: 249241
Revision Number: 010
Revision Date: 30-May-2006
Figure 46. SS-SMII - 100BASE-TX Transmit Timing
Table 67. SS-SMII - 100BASE-TX Transmit Timing
TxSYNC setup to TxCLK rising edge and
TxData setup to TxCLK rising edge
TxSYNC hold from TxCLK rising edge and
TxData hold to TxCLK rising edge
TxEN sampled to start of /J/
NOTE: The table latency values are derived with the hardware configuration pins FIFOSEL[1:0] set at a
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
2. “BT” signifies bit times at the line rate (that is, BT = 100 ns if using 10BASE-T, BT = 10 ns if using
testing.
100BASE-TX or 100BASE-FX).
default configuration of 00 (32 bits of initial fill).
TxSYNC
TxData
TxCLK
TPFO
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Parameter
t
1
t
2
t
3
Sym
t1
t2
t3
Min
1.5
1.0
Typ
t
1
11
1
t
2
Max
18
Units
BT
ns
ns
2
Conditions
Test
185

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