DP83848CVVX National Semiconductor, DP83848CVVX Datasheet - Page 10

• Manufacturer Part Number: DP83848CVVX
• Manufacturer: National Semiconductor

Specifications of DP83848CVVX

• Lead Free Status / RoHS Status: Compliant

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RX_CLK
RX_DV
RX_ER
RXD_0
RXD_1
RXD_2
RXD_3
CRS/CRS_DV
COL
Signal Name
S, O, PU
S, O, PD
S, O, PU
S, O, PU
S, O, PD
Type
O
Pin #
38
39
41
43
44
45
46
40
42
MII RECEIVE CLOCK: Provides the 25 MHz recovered receive
clocks for 100 Mb/s mode and 2.5 MHz for 10 Mb/s mode.
Unused in RMII mode. The device uses the X1 reference clock in-
put as the 50 MHz reference for both transmit and receive.
SNI RECEIVE CLOCK: Provides the 10 MHz recovered receive
clocks for 10 Mb/s SNI mode.
MII RECEIVE DATA VALID: Asserted high to indicate that valid
data is present on the corresponding RXD[3:0]. MII mode by de-
fault with internal pulldown.
RMII Synchronous Receive Data Valid: This signal provides the
RMII Receive Data Valid indication independent of Carrier Sense.
This pin is not used in SNI mode.
MII RECEIVE ERROR: Asserted high synchronously to RX_CLK
to indicate that an invalid symbol has been detected within a re-
ceived packet in 100 Mb/s mode.
RMII RECEIVE ERROR: Assert high synchronously to X1 when-
ever it detects a media error and RXDV is asserted in 100 Mb/s
mode.
This pin is not required to be used by a MAC, in either MII or RMII
mode, since the Phy is required to corrupt data on a receive error.
This pin is not used in SNI mode.
MII RECEIVE DATA: Nibble wide receive data signals driven syn-
chronously to the RX_CLK, 25 MHz for 100 Mb/s mode, 2.5 MHz
for 10 Mb/s mode). RXD[3:0] signals contain valid data when
RX_DV is asserted.
RMII RECEIVE DATA: 2-bits receive data signals, RXD[1:0], driv-
en synchronously to the X1 clock, 50 MHz.
SNI RECEIVE DATA: Receive data signal, RXD_0, driven syn-
chronously to the RX_CLK. RXD_0 contains valid data when CRS
is asserted. RXD[3:1] are not used in this mode.
MII CARRIER SENSE: Asserted high to indicate the receive me-
dium is non-idle.
RMII CARRIER SENSE/RECEIVE DATA VALID: This signal
combines the RMII Carrier and Receive Data Valid indications.
For a detailed description of this signal, see the RMII Specifica-
tion.
SNI CARRIER SENSE: Asserted high to indicate the receive me-
dium is non-idle. It is used to frame valid receive data on the
RXD_0 signal.
MII COLLISION DETECT: Asserted high to indicate detection of
a collision condition (simultaneous transmit and receive activity)
in 10 Mb/s and 100 Mb/s Half Duplex Modes.
While in 10BASE-T Half Duplex mode with heartbeat enabled this
pin is also asserted for a duration of approximately 1 s at the end
of transmission to indicate heartbeat (SQE test).
In Full Duplex Mode, for 10 Mb/s or 100 Mb/s operation, this sig-
nal is always logic 0. There is no heartbeat function during 10
Mb/s full duplex operation.
RMII COLLISION DETECT: Per the RMII Specification, no COL
signal is required. The MAC will recover CRS from the CRS_DV
signal and use that along with its TX_EN signal to determine col-
lision.
SNI COLLISION DETECT: Asserted high to indicate detection of
a collision condition (simultaneous transmit and receive activity)
in 10 Mb/s SNI mode.
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Description