DP83848CVVX National Semiconductor, DP83848CVVX Datasheet - Page 56

• Manufacturer Part Number: DP83848CVVX
• Manufacturer: National Semiconductor

Specifications of DP83848CVVX

• Lead Free Status / RoHS Status: Compliant

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7.2.7 RMII and Bypass Register (RBR)
This register configures the RMII Mode of operation. When RMII mode is disabled, the RMII functionality is bypassed.
7.2.8 LED Direct Control Register (LEDCR)
This register provides the ability to directly control any or all LED outputs. It does not provide read access to LEDs.
15:6
15:6
Bit
1:0
Bit
5
4
3
2
5
4
3
2
1
0
ELAST_BUF[1:0]
DRV_SPDLED
DRV_ACTLED
RX_OVF_STS
RX_UNF_STS
DRV_LNKLED
RMII_REV1_0
RMII_MODE
RESERVED
RESERVED
Bit Name
Bit Name
SPDLED
LNKLED
ACTLED
Table 28. LED Direct Control Register (LEDCR), address 0x18
Table 27. RMII and Bypass Register (RBR), addresses 0x17
Strap, RW
Default
Default
01, RW
0, RW
0, RW
0, RW
0, RW
0, RW
0, RW
0, RW
0, RO
0, RO
0, RO
0, RO
RESERVED: Writes ignored, read as 0.
Reduced MII Mode:
0 = Standard MII Mode
1 = Reduced MII Mode
Reduce MII Revision 1.0:
0 = (RMII revision 1.2) CRS_DV will toggle at the end of a packet
to indicate deassertion of CRS.
1 = (RMII revision 1.0) CRS_DV will remain asserted until final data
is transferred. CRS_DV will not toggle at the end of a packet.
RX FIFO Over Flow Status:
0 = Normal
1 = Overflow detected
RX FIFO Under Flow Status:
0 = Normal
1 = Underflow detected
Receive Elasticity Buffer. This field controls the Receive Elastic-
ity Buffer which allows for frequency variation tolerance between
the 50MHz RMII clock and the recovered data. The following val-
ues indicate the tolerance in bits for a single packet. The minimum
setting allows for standard Ethernet frame sizes at +/-50ppm accu-
racy for both RMII and Receive clocks. For greater frequency tol-
erance the packet lengths may be scaled (i.e. for +/-100ppm, the
packet lengths need to be divided by 2).
00 = 14 bit tolerance (up to 16800 byte packets)
01 = 2 bit tolerance (up to 2400 byte packets)
10 = 6 bit tolerance (up to 7200 byte packets)
11 = 10 bit tolerance (up to 12000 byte packets)
RESERVED: Writes ignored, read as 0.
1 = Drive value of SPDLED bit onto LED_SPD output
0 = Normal operation
1 = Drive value of LNKLED bit onto LED_LNK output
0 = Normal operation
1 = Drive value of ACTLED bit onto LED_ACT/COL output
0 = Normal operation
Value to force on LED_SPD output
Value to force on LED_LNK output
Value to force on LED_ACT/COL output
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Description
Description