DP83848CVVX National Semiconductor, DP83848CVVX Datasheet - Page 52

• Manufacturer Part Number: DP83848CVVX
• Manufacturer: National Semiconductor

Specifications of DP83848CVVX

• Lead Free Status / RoHS Status: Compliant

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7.2.2 MII Interrupt Control Register (MICR)
This register implements the MII Interrupt PHY Specific Control register. Sources for interrupt generation include: Energy
Detect State Change, Link State Change,
any of the counters becoming half-full. The individual interrupt events must be enabled by setting bits in the MII Inter-
rupt Status and Event Control Register (MISR)
15:3
Bit
2
1
0
Bit Name
Reserved
INT_OE
INTEN
TINT
Table 22. MII Interrupt Control Register (MICR), address 0x11
Default
0, RW
0, RW
0, RW
0, RO
Speed Status Change, Duplex Status Change, Auto-Negotiation Complete or
.
Reserved: Write ignored, Read as 0
Test Interrupt:
Forces the PHY to generate an interrupt to facilitate interrupt test-
ing. Interrupts will continue to be generated as long as this bit re-
mains set.
1 = Generate an interrupt
0 = Do not generate interrupt
Interrupt Enable:
Enable interrupt dependent on the event enables in the MISR reg-
ister.
1 = Enable event based interrupts
0 = Disable event based interrupts
Interrupt Output Enable:
Enable interrupt events to signal via the PWR_DOWN/INT pin by
configuring the PWR_DOWN/INT pin as an output.
1 = PWR_DOWN/INT is an Interrupt Output
0 = PWR_DOWN/INT is a Power Down Input
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Description