DP83848CVVX National Semiconductor, DP83848CVVX Datasheet - Page 77

• Manufacturer Part Number: DP83848CVVX
• Manufacturer: National Semiconductor

Specifications of DP83848CVVX

• Lead Free Status / RoHS Status: Compliant

8.2.23 100BASE-TX Signal Detect Timing
Note: The signal amplitude on PMD Input Pair must be TP-PMD compliant.
8.2.24 100 Mb/s Internal Loopback Timing
Note1: Due to the nature of the descrambler function, all 100BASE-TX Loopback modes will cause an initial “dead-time”
of up to 550 s during which time no data will be present at the receive MII outputs. The 100BASE-TX timing specified is
based on device delays after the initial 550 s “dead-time”.
Note2: Measurement is made from the first rising edge of TX_CLK after assertion of TX_EN.
T2.23.1
T2.23.2
T2.24.1
Parameter
Parameter
PMD Input Pair
SD+ internal
RXD[3:0]
TXD[3:0]
TX_CLK
RX_CLK
SD Internal Turn-on Time
SD Internal Turn-off Time
TX_EN to RX_DV Loopback
TX_EN
RX_DV
CRS
Description
Description
T2.23.1
T2.24.1
100 Mb/s internal loopback mode
77
Notes
Notes
T2.23.2
Min
Min
Typ
Typ
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Max
Max
350
240
1
Units
Units
ms
ns
s