82V1074PFG IDT, Integrated Device Technology Inc, 82V1074PFG Datasheet - Page 26

• Manufacturer Part Number: 82V1074PFG
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82V1074PFG

• Number Of Channels: 4
• On-hook Transmission: Yes
• Polarity Reversal: Yes
• On-chip Ring Relay Driver: Yes
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TQFP
• Operating Temperature Classification: Industrial
• Pin Count: 100
• Mounting: Surface Mount
• Operating Current: 95mA
• Operating Supply Voltage (max): 3.465V
• Operating Supply Voltage (min): 3.135V
• Lead Free Status / RoHS Status: Compliant

Table - 3 Registers and Coe-RAM Locations Used for External Ringing Mode
CODEC and RSLIC Operating Mode
Configuration
External Ring Relay Control
(recommended)
Synchronous Mode Enable Bit
External Ring Trip Detection Source
External Ring Trip Threshold
External Ring Trip Detection Result
Indication
Level Meter Configuration and Result
Registers
DC Offset Compensation
RSLIC & CODEC CHIPSET
7. Disable the rectifier (LREG10: LM_RECT = 0);
8. Set the gain factor as required (LREG10: LM_GF);
9. Set the level meter measurement mode to ONCE and start the
10.Read the measurement result from GREG17 & GREG18 (16-bit);
11. Right shift the 16-bit result for two bits, then the result is the offset
12.Invert each bit of the offset value and add 1 to it, write this result to
measurement (GREG16: LM_ONCE = 1, LM_EN = 1);
value in the form of a 14-bit two’s complement;
Parameter
MPI mode: bits ACTIVE, SCAN_EN and SM[2:0]
in LREG6;
GCI mode: bit ACTIVE in LREG6, bits SCAN_EN
and SM[2:0] in downstream C/I channel byte.
Bit IO_C[0] in LREG20
Bit IO[0] in LREG20
Bit SYNC_EN in LREG19
Bit LM_SEL[3:0] in LREG9
Word HKthld in the Coe-RAM
Bits HK[n] in GREG26
LREG8: LM_SRC, DC_SRC
LREG9: K[3:0]
LREG10: LM_GF, LM_RECT
GREG15 & GREG16
GREG17 & GREG18
Bit DC_OFT in LREG4
Word DC Offset in the Coe-RAM
Register Bits
26
be more reliably detected.
external ringing mode.
13.Select this offset compensation value to be used (LREG4:
14.Restore the modified registers with original contents;
Then, the four steps mentioned above follow and off-hook event will
Table - 3
ACTIVE = 1: the CODEC is set to Active mode
SCAN_EN = 1 and SM[2:0] = 001: the RLSIC is set to External Ringing
mode.
IO_C[0] = 1: the IO1 pin is configured as an output
IO[0] = 0: the IO1 pin is set to logic low
IO[0] = 1: the IO1 pin is set to logic high
SYNC_EN = 0: asynchronous mode is selected
SYNC_EN = 1: synchronous mode is selected
LM_SEL[3:0] = 1100: RTIN is selected to the DC path for ring trip detection
If the Signaling bit in LREG5 is set to 1, the external ring trip threshold in
the ROM is selected, otherwise the threshold written in HKthld in the Coe-
RAM is selected.
The HKthld in the Coe-RAM is programmable from 0 to 20 mA with
tolerance. The default value (in the ROM) is 7 mA.
Note that both the off-hook detection threshold in active mode and the
external ring trip threshold are written in HKthld in the Coe-RAM. Users
should change the threshold according to different conditions.
Indicating the ring trip detection result, ‘0’ means Channel n+1 is on-hook
while ‘1’ means Channel n+1 is off-hook (n = 0 to 3).
Refer to
DC_OFT = 0: compensation value in word DC Offset in the Coe-RAM is
selected;
DC_OFT = 1: compensation value (which is 0) in the ROM is selected
(default).
DC Offset in the Coe-RAM.
DC_OFT = 0);
Table - 17 on page 44
shows the registers and Coe-RAM locations used for
IDT82V1671/IDT82V1671A, IDT82V1074
for details.
Notes
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