82V1074PF IDT, Integrated Device Technology Inc, 82V1074PF Datasheet - Page 24

• Manufacturer Part Number: 82V1074PF
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82V1074PF

• Number Of Channels: 4
• On-hook Transmission: Yes
• Polarity Reversal: Yes
• On-chip Ring Relay Driver: Yes
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TQFP
• Operating Temperature Classification: Industrial
• Pin Count: 100
• Mounting: Surface Mount
• Operating Current: 95mA
• Operating Supply Voltage (max): 3.465V
• Operating Supply Voltage (min): 3.135V
• Lead Free Status / RoHS Status: Not Compliant

to 1 to indicate off-hook detected. An interrupt will be generated if the
HK[n] bit is not masked.
be detected by the AC ring trip. When the off-hook condition is detected
during a ring burst period, the ringing signal will be removed
automatically at zero-crossing. As the RING_EN bit remains unchanged,
users should clear it to 0 by software.
Table - 2 Registers and Coe-RAM Locations Used for Internal Ringing Mode
3.4.2
applications of requiring higher ring amplitudes, external ringing signals
can be used.
use an external ringing signal.
details), the ringing signal from an external ring generator will be
switched to the Tip/Ring lines through an external relay during ring burst
period, and will be removed during ring pause period.
relay-driving capability for each channel. They can be used to control the
external ring relay without additional components. The external ringing
can be switched on/off in two different modes as described below:
selected to control the external ring relay). In this mode, the external
ringer provides a synchronous signal for the CODEC via the RSYNC pin
to ensure switching the ringing signal at zero-crossing. This
synchronous mode is enabled by setting the SYNC_EN bit in LREG19 to
1. When the IO1 pin of the CODEC is configured as an output (LREG20:
Internal Ringing Mode Selection
Internal Ringing Enable
Internal Ringing Parameters
Selection
Internal Ringing Frequency
Internal Ringing Amplitude
Internal Ringing Offset Voltage
Ring Trip Method Selection
Ring Trip Threshold Selection
AC Ring Trip Threshold
DC Ring Trip Threshold
Ring Trip Detection Result
Indication
RSLIC & CODEC CHIPSET
Note that during a ring pause period, the off-hook condition can not
If several telephones are in parallel with each other between the Tip
The chipset can generate internal ringing signals of up to 70 Vp. In
If the RSLIC is set to External Ringing mode (see
The CODEC provides two programmable IO pins (IO1 and IO2) with
• Synchronous mode (this mode is available when the IO1 pin is
Parameter
EXTERNAL RINGING MODE
Figure - 50 on page 105
MPI mode: bit RING in LREG7, bits
SCAN_EN and SM[2:0] in LREG6;
GCI mode: bit RING in LREG7, bits
SCAN_EN and SM[2:0] in downstream C/I
channel byte.
Bit RING_EN in LREG7
Bit RG in LREG5
Word RingFreq in the Coe-RAM
Word RingAmp in the Coe-RAM
Word RingOffset in the Coe-RAM
Bit RT_SEL in LREG7
Bit Signaling in LREG5
Word RTthld_AC in the Coe-RAM
Word RTthld_DC in the Coe-RAM
Bits HK[n] in GREG26
Register Bits/Coe-RAM Words
shows an application circuit that
Table - 3
for
RING = 1: the CODEC is set to Ring mode
SCAN_EN = 1 and SM[2:0] = 010: the RLSIC is set to Internal Ringing mode.
RING_EN = 0: ring pause;
RING_EN = 1: ring burst.
RG = 0: ringing parameters in the Coe-RAM are selected.
RG = 1: ringing parameters (frequency, amplitude and offset) in the ROM are
selected (default);
Programmable via the Coe-RAM. Programmable range: 20 to 200 Hz with
tolerance. Default value (in the ROM): 30 Hz.
Programmable via the Coe-RAM. Programmable range: 0 to 70 Vp with
tolerance. Default value (in the ROM): 40 Vp.
Programmable via the Coe-RAM. Programmable range: 0 to 20 V with
tolerance. Default value (in the ROM): 7 V.
RT_SEL = 0: AC ring trip is selected;
RT_SEL = 1: DC ring trip is selected.
Signaling = 0: The AC and DC ring trip thresholds in the Coe-RAM are selected;
Signaling = 1: The AC and DC ring trip thresholds in the ROM are selected (default);
Programmable via the Coe-RAM. Programmable range: 0 to 20 mA with
tolerance. Default value (in the ROM): 5 mA.
Programmable via the Coe-RAM. Programmable range: 0 to 20 mA with
tolerance. Default value (in the ROM): 5 mA.
Indicating the ring trip detection result, ‘0’ means Channel n+1 is on-hook while ‘1’
means Channel n+1 is off-hook (n = 0 to 3)
24
and Ring lines, the on-hook AC current will increase. If the AC load is
too large, the on-hook current of short loop will be larger than the off-
hook current of long loop - this will possibly cause a false indication of
the off-hook condition. Consequently, the AC ring trip detection method
should only be used in short loops (loop impedance < 1 kΩ) and low-
power applications.
generation and ring trip detection.
IO_C[0] = 1), the external ringing signal will be switched on the RSYNC
edge (rising or falling) next to the change of the IO1 pin, as illustrated in
Figure -
LREG20:
function to speed up the response of off-hook event. For example, if a
logic low on the IO1 pin starts the ringing while a logic high on this pin
stops the ringing, once an off-hook event is detected during ring burst
period, the IO1 pin will be set to logic high automatically to remove the
ringing signal although the IO[0] bit remains 0. Users should set the
IO[0] bit to 1 by software.
RSYNC pin of the CODEC, or some applications need to switch the
ringing signal without any delay caused by zero-crossing
synchronization, the SYNC_EN bit in LREG19 should be set to 0. In this
case, the external ringing signal will be switched immediately after the
corresponding IO pin control bit (IO[0] for the IO1 pin and IO[1] for the
Table - 2
IO[0] = 0: IO1 pin is set to logic low;
IO[0] = 1: IO1 pin is set logic high.
In synchronous mode, the CODEC provides a hardware ring trip
• Asynchronous mode. If no synchronous signal is applied to the
12. The logic level of the IO1 pin is set by the IO[0] bit in
lists the programmable parameters used for internal ringing
IDT82V1671/IDT82V1671A, IDT82V1074
Notes
±
±
1%
±
±
1%
5%
5%
±
3%