82V1074PF IDT, Integrated Device Technology Inc, 82V1074PF Datasheet - Page 93

• Manufacturer Part Number: 82V1074PF
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82V1074PF

• Number Of Channels: 4
• On-hook Transmission: Yes
• Polarity Reversal: Yes
• On-chip Ring Relay Driver: Yes
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TQFP
• Operating Temperature Classification: Industrial
• Pin Count: 100
• Mounting: Surface Mount
• Operating Current: 95mA
• Operating Supply Voltage (max): 3.465V
• Operating Supply Voltage (min): 3.135V
• Lead Free Status / RoHS Status: Not Compliant

6.6
≤
Figure - 50 on page
sequence is not necessary.
6.7
6.8
6.8.1
hardware reset of the CODEC can be accomplished by setting the signal
to the RESET pin to low level for at least 50 µs or setting the HW_RST
bit in GREG5 to 1. After a power-on reset or a hardware reset, the
default register settings are used. The CODEC will then enter the default
state as described below:
RSLIC & CODEC CHIPSET
VBL
RSLIC power on sequence is as follows:
1. Apply Ground to the AGND and BGND pins;
2. Apply +3.3 V power supply to the VDD pin;
3. Apply battery voltage to the VBH pin;
4. Apply battery voltage to the VBL pin.
Please note thatVBH and VBL voltage ranges are as follows:
IDT82V1671A:
IDT82V1671:
If the recommended application circuit
CODEC power on sequence is as follows:
1. Apply Ground to all ground pins;
2. Apply VDD voltage to all power supply pins;
3. Select master clock frequency (via GREG4);
4. Program filter coefficients and other parameters as required.
The CODEC can be reset by a power-on reset or a hardware reset. A
1. All four channels are powered down;
2. All loopbacks and cutoff are disabled;
3. The DX1/DU pin is selected for all channels to transmit PCM
4. The master clock (MCLK) frequency is 2.048 MHz;
5. In MPI mode, Time Slot 0 to Time Slot 3 are selected for Channel
data. The DR1/DD pin is selected for all channels to receive PCM
data.
1 to Channel 4 to transmit and receive data. The PCM data rate is
the same as the Bit Clock (BCLK) frequency. The PCM data is
RSLIC POWER ON SEQUENCE
CODEC POWER ON SEQUENCE
DEFAULT STATE AFTER RESET
POWER-ON RESET AND HARDWARE RESET
−
52 V
−
70 V
105) is used, the above mentioned RSLIC power on
≤
≤
VBH
VBH
≤ −
≤ −
20 V,
52 V,
−
52 V
−
(Figure - 49 on page 104
52 V
≤
≤
VBL
VBL
≤ −
≤ −
20 V, and VBH
20 V
or
93
6.8.2
reset command. The RCH_SEL[3:0] bits in GREG5 determine whether
Channel 4 to Channel 1 will be software reset or not. Setting the
SW_RST bit and any desired bit of RCH_SEL[3:0] to 1 will reset the
corresponding channel. Once a software reset is performed, the device
will enter the following state:
6. A-law is selected;
7. Default register settings are selected;
8. All IO pins are configured as inputs;
9. All maskable interrupts are masked by corresponding mask bits;
10.All function blocks including level meter, UTD unit, FSK generator,
Each channel of the CODEC can be individually reset by a software
1. The reset channel(s) are powered down;
2. All test loopbacks and cutoff on the reset channel(s) are disabled;
3. The DX1/DU and DR1/DD pins are selected for the reset
4. In MPI mode, Time Slot 0 to Time Slot 3 are selected for Channel
5. All default coefficients and register setting except the highpass
6. All IO pins of the reset channel(s) are configured as inputs;
7. All maskable interrupts of the reset channel(s) are masked by
transmitted on the rising edges of BCLK and received on the
falling edges of BCLK.
In GCI mode, time slot assignment is determined by the logic
levels of the CCLK/S0 and CI/S1 pins. The data rate is always
2.048 MHz, no matter 2.048 MHz or 4.096 MHz is applied to the
DCL pin. The GCI data is transferred via the DU/DD pin on rising
edges of DCL.
tone generators etc., are disabled.
channel(s) to transmit and receive PCM data.
1 to Channel 4 to transmit and receive the PCM data. The PCM
data rate is the same as the Bit Clock (BCLK) frequency. The
PCM data is transmitted on the rising edges of BCLK and
received on the falling edges.
In GCI mode, time slot assignment is determined by the logic
levels of the CCLK/S0 and CI/S1 pins. The data rate is always
2.048 MHz, no matter 2.048 MHz or 4.096 MHz is applied to the
DCL pin. The GCI data is transferred via DU/DD pin on rising
edges of DCL.
filter (the HPF bit in LREG5 is set to 1) are selected for the reset
channel(s).
corresponding mask bits.
SOFTWARE RESET
IDT82V1671/IDT82V1671A, IDT82V1074