LMP90100MHE National Semiconductor, LMP90100MHE Datasheet - Page 21

• Manufacturer Part Number: LMP90100MHE
• Description: AFE, SENSOR, 28TSSOP
• Manufacturer: National Semiconductor

Specifications of LMP90100MHE

• Brief Features: 24bit Low Power Sigma Delta ADC, Automatic Channel Sequencer
• Supply Voltage Range: 2.7V To 5.5V
• Operating Temperature Range: -40°C To +105°C
• Digital Ic Case Style: TSSOP
• No. Of Pins: 28
• Base: RoHS Compliant
• Ic Function: Multi-Channel, Low Power 24-bit Sensor AFE
• Rohs Compliant: Yes

16.0 Functional Description
The LMP90100 is a low-power 24-Bit ΣΔ ADC with 4 fully dif-
ferential or 7 single-ended analog channels. Its serial data
output is two’s complement format. The output data rate
(ODR) ranges from 1.6775 SPS to 214.65 SPS.
The serial communication for LMP90100 is SPI, a syn-
chronous serial interface that operates using 4 pins: chip
select bar (CSB), serial clock (SCLK), serial data in (SDI), and
serial data out / data ready bar (SDO/DRYDYB).
True continuous built-in offset and gain background calibra-
tion is also available to improve measurement accuracy. Un-
like other ADCs, the LMP90100’s background calibration can
run without interrupting the input signal. This unique tech-
nique allows for positive as well as negative gain calibration
and is available at all gain settings.
The registers can be found in
detailed description of the LMP90100 are provided in the fol-
lowing sections.
16.1 SIGNAL PATH
16.1.1 Reference Input (VREF)
The differential reference voltage VREF (VREFP – VREFN)
sets the range for VIN.
The muxed VREF allows the user to choose between VREF1
or VREF2 for each channel. This selection can be made by
16.1.3 Selectable Gains (FGA & PGA)
LMP90100 provides two types of gain amplifiers: a fixed gain
amplifier (FGA) and a programmable gain amplifier (PGA).
FGA has a fixed gain of 16x or it can be bypassed, while the
PGA has programmable gain settings of 1x, 2x, 4x, or 8x.
Section 18.0
Registers, and a
FIGURE 3. Simplified VIN Circuitry
21
programming the VREF_SEL bit in the CHx_INPUTCN reg-
isters (CHx_INPUTCN: VREF_SEL). The default mode is
VREF1. If VREF2 is used, then VIN6 and VIN7 cannot be
used as inputs because they share the same pin.
Refer to
mation.
16.1.2 Flexible Input MUX (VIN)
LMP90100 provides a flexible input MUX as shown in
3. The input that is digitized is VIN = VINP – VINN; where
VINP can be any of the VIN0 to VIN7 input, and VINN can be
any of the VIN0 to VIN7 input.
The digitized input is also known as a channel, where
CH = VIN = VINP – VINN. Thus, there are a maximum of 4
differential channels: CH0, CH1, CH2, and CH3.
LMP90100 can also be configured single-endedly, where the
common ground is any one of the VIN0 to VIN7 inputs. There
are a maximum of 7 single-ended channels: CH0, CH1, CH2,
CH3, CH4, CH5, and CH6.
The input MUX can be programmed in the CHx_INPUTCN
registers. For example, to program CH0 = VIN = VIN4 – VIN1,
go to the CH0_INPUTCN register and set:
1. VINP = 0x4
2. VINN = 0x1
Total gain is defined as FGA x PGA. Thus, LMP90100 pro-
vides gain settings of 1x, 2x, 4x, 8x, 16x, 32x, 64x, or 128x
with true continuous background calibration.
The gain is channel specific, which means that one channel
can have one gain, while another channel can have the same
or a different gain.
Section 17.2.2 VREF
for VREF applications infor-
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Figure