LMP90100MHE National Semiconductor, LMP90100MHE Datasheet - Page 35

• Manufacturer Part Number: LMP90100MHE
• Description: AFE, SENSOR, 28TSSOP
• Manufacturer: National Semiconductor

Specifications of LMP90100MHE

• Brief Features: 24bit Low Power Sigma Delta ADC, Automatic Channel Sequencer
• Supply Voltage Range: 2.7V To 5.5V
• Operating Temperature Range: -40°C To +105°C
• Digital Ic Case Style: TSSOP
• No. Of Pins: 28
• Base: RoHS Compliant
• Ic Function: Multi-Channel, Low Power 24-bit Sensor AFE
• Rohs Compliant: Yes

Note that while being in the data first mode, once the data
bytes in the data only read transaction are sent out, the device
is ready to start on any normal (non-data-only) transaction
including the disable data first mode instruction. The current
status of the data first mode (enabled/disabled status) can be
read back using the read mode status transaction. This trans-
action consists of the read mode status instruction followed
by a single data byte (driven by the device). The data first
mode status is available on bit [1] of this data byte.
The data only read transaction allows reading up to eight
consecutive registers, starting from any start address. Usu-
ally, the start address will be the address of the most signifi-
cant byte of conversion data, but it could just as well be any
other address. The start address and number of bytes to be
read during the data only read transaction can be pro-
grammed using the DATA_ONLY_1 AND DATA_ONLY_2
registers respectively.
The upper register address is unaffected by a data only read
transaction. That is, it retains its setting even after encoun-
tering a data only transaction. The data only transaction uses
its own address (including the upper address) from the
DATA_ONLY_1 register. When in the data first mode, the
SCLK must stop high before entering the data only read
transaction.
Enable Data First Mode Instruction
Disable Data First Mode Instruction
Read Mode Status Instruction
FIGURE 24. Timing Protocol for Reading SPI_CRC_DAT
TABLE 6. Data First Mode Transactions
Bit[7]
1
1
1
35
Bits[6:5]
11
11
00
16.5.7 Cyclic Redundancy Check (CRC)
CRC can be used to ensure integrity of data transfer. To en-
able CRC, set EN_CRC high. Once CRC is enabled, the CRC
value is calculated and stored in SPI_CRC_DAT so that the
master device can periodically read for data comparison.
Conveniently, the SPI_CRC_DAT register address is located
next to the ADC_DOUT register address so that the CRC val-
ue can be easily read as part of the data set. The CRC is
automatically reset when CSB or DRDYB is deasserted.
The CRC format for LMP90100 is x
value of the SPI_CRC_DAT register is zero, and the final val-
ue is ones-complemented before it is sent out. Note that CRC
computation only includes the bits sent out on SDO and does
not include the bits of the SPI_CRC_DAT itself; thus it is okay
to read SPI_CRC_DAT repeatedly.
The drdyb signal normally deasserts (active high) every 1/
ODR second or when the LSB of ADC_DOUTL is read. How-
ever, this behavior can be changed so that drdyb deassertion
can occur after SPI_CRC_DAT is read. This is done by setting
bit DRDYB_AFT_CRC high.
The timing protocol for CRC can be found in the following fig-
ure.
Bit[4]
1
1
1
Bits[3:0]
1010
1011
1111
8
+ x
5
Data Bytes
None
None
One
+ x
4
+ 1. The reset
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