LMP90100MHE National Semiconductor, LMP90100MHE Datasheet - Page 37

• Manufacturer Part Number: LMP90100MHE
• Description: AFE, SENSOR, 28TSSOP
• Manufacturer: National Semiconductor

Specifications of LMP90100MHE

• Brief Features: 24bit Low Power Sigma Delta ADC, Automatic Channel Sequencer
• Supply Voltage Range: 2.7V To 5.5V
• Operating Temperature Range: -40°C To +105°C
• Digital Ic Case Style: TSSOP
• No. Of Pins: 28
• Base: RoHS Compliant
• Ic Function: Multi-Channel, Low Power 24-bit Sensor AFE
• Rohs Compliant: Yes

17.0 Applications Information
17.1 QUICK START
This section shows step-by-step instructions to configure the
LMP90100 to perform a simple DC reading from CH0.
1.
2.
3.
4.
5.
6.
7.
8.
17.2 CONNECTING THE SUPPLIES
17.2.1 VA and VIO
Any ADC architecture is sensitive to spikes on the analog
voltage, VA, digital input/output voltage, VIO, and ground
pins. These spikes may originate from switching power sup-
plies, digital logic, high power devices, and other sources. To
diminish these spikes, the LMP90100’s VA and VIO pins
should be clean and well bypassed. A 0.1 µF ceramic bypass
capacitor and a 1 µF tantalum capacitor should be used to
bypass the LMP90100 supplies, with the 0.1 µF capacitor
placed as close to the LMP90100 as possible.
Since the LMP90100 has both external VA and VIO pins, the
user has two options on how to connect these pins. The first
option is to tie VA and VIO together and power them with the
same power supply. This is the most cost effective way of
powering the LMP90100 but is also the least ideal because
noise from VIO can couple into VA and negatively affect per-
formance. The second option involves powering VA and VIO
with separate power supplies. These supply voltages can
have the same amplitude or they can be different.
17.2.2 VREF
Operation with VREF below VA is also possible with slightly
diminished performance. As VREF is reduced, the range of
acceptable analog input voltages is also reduced. Reducing
the value of VREF also reduces the size of the LSB. When
the LSB size goes below the noise floor of the LMP90100, the
noise will span an increasing number of codes and perfor-
mance will degrade. For optimal performance, VREF should
Apply VA = VIO = VREFP1 = 5V, and ground VREFN1
Apply VINP = ¾VREF and VINN = ¼VREF for CH0.
Thus, set CH0 = VIN = VINP - VINN = ½VREF
(CH0_INPUTCN register)
Set gain = 1 (CH0_CONFIG: GAIN_SEL = 0x0)
Exclude the buffer from the signal path (CH0_CONFIG:
BUF_EN = 1)
Set the background to BgcalMode2 (BGCALCN = 0x2)
Select VREF1 (CH0_INPUTCN: VREF_SEL = 0)
To use the internal CLK, set CLK_EXT_DET = 1 and
CLK_SEL = 0.
Follow the register read/write protocol
capture ADC_DOUT from CH
(Figure
17) to
37
be the same as VA and sourced with a clean source that is
bypassed with a ceramic capacitor value of 0.1 µF and a tan-
talum capacitor of 10 µF.
LMP90100 also allows ratiometric connection for noise im-
munity reasons. A ratiometric connection is when the ADC’s
VREFP and VREFN are used to excite the input device’s (i.e.
a bridge sensor) voltage references. This type of connection
severely attenuates any VREF ripple seen the ADC output,
and is thus strongly recommended.
17.3 ADC_DOUT CALCULATION
The output code of the LMP90100 can be calculated as:
ADC_DOUT is in 24−bit two's complement binary format. The
largest positive value is 0x7F_FFFF while the largest negative
value is 0x80_0000. In case of an over range the value is
automatically clamped to one of these two values.
Figure 26
analog input voltage, VIN, using the equation above.
FIGURE 26. ADC_DOUT vs. VIN of a 24-Bit Resolution
shows the theoretical output code, ADC_DOUT, vs.
Equation 1 — Output Code
(VREF = 5.5V, Gain = 1).
www.national.com
30139547