PIC16LF1906-E/MV Microchip Technology, PIC16LF1906-E/MV Datasheet - Page 172

• Manufacturer Part Number: PIC16LF1906-E/MV
• Description: 14KB Flash, 512B RAM, LCD, 11x10b ADC, EUSART, NanoWatt XLP 28 UQFN 4x4x0.5mm TU
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16LF1906-E/MV

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: LIN, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 14KB (8K x 14)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-UFQFN Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC16LF1904/6/7
18.3.1
The EUSART module supports automatic detection
and calibration of the baud rate.
In the Auto-Baud Detect (ABD) mode, the clock to the
BRG is reversed. Rather than the BRG clocking the
incoming RX signal, the RX signal is timing the BRG.
The Baud Rate Generator is used to time the period of
a received 55h (ASCII “U”) which is the Sync character
for the LIN bus. The unique feature of this character is
that it has five rising edges including the Stop bit edge.
Setting the ABDEN bit of the BAUDCON register starts
the auto-baud calibration sequence
While the ABD sequence takes place, the EUSART
state machine is held in Idle. On the first rising edge of
the receive line, after the Start bit, the SPBRGL begins
counting up using the BRG counter clock as shown in
Table
RX/DT pin at the end of the eighth bit period. At that
time, an accumulated value totaling the proper BRG
period is left in the SPBRGH:SPBRGL register pair, the
ABDEN bit is automatically cleared, and the RCIF
interrupt flag is set. A read operation on the RCREG
needs to be performed to clear the RCIF interrupt.
RCREG content should be discarded. When calibrating
for modes that do not use the SPBRGH register the
user can verify that the SPBRGL register did not
overflow by checking for 00h in the SPBRGH register.
The BRG auto-baud clock is determined by the BRG16
and BRGH bits as shown in
both the SPBRGH and SPBRGL registers are used as
a 16-bit counter, independent of the BRG16 bit setting.
While calibrating the baud rate period, the SPBRGH
FIGURE 18-6:
DS41569A-page 172
BRG Value
BRG Clock
ABDEN bit
RX/DT pin
RCIF bit
(Interrupt)
SPBRGH
SPBRGL
RCREG
18-6. The fifth rising edge will occur on the
RCIDL
Note 1:
Read
AUTO-BAUD DETECT
Set by User
The ABD sequence requires the EUSART module to be configured in Asynchronous mode.
XXXXh
AUTOMATIC BAUD RATE CALIBRATION
Table
0000h
18-6. During ABD,
(Figure
Start
18.3.2).
bit 0
XXh
XXh
Edge #1
Preliminary
bit 1
bit 2
Edge #2
and SPBRGL registers are clocked at 1/8th the BRG
base clock rate. The resulting byte measurement is the
average bit time when clocked at full speed.
TABLE 18-6:
BRG16
Note:
Note 1: If the WUE bit is set with the ABDEN bit,
bit 3
0
0
1
1
2: It is up to the user to determine that the
3: During the auto-baud process, the
bit 4
Edge #3
BRGH
During the ABD sequence, SPBRGL and
SPBRGH registers are both used as a
16-bit counter, independent of BRG16
setting.
auto-baud detection will occur on the byte
following the Break character (see
Section 18.3.3
Break”).
incoming character baud rate is within the
range of the selected BRG clock source.
Some combinations of oscillator frequency
and EUSART baud rates are not possible.
auto-baud counter starts counting at 1.
Upon
sequence, to achieve maximum accu-
racy,
SPBRGH:SPBRGL register pair.
0
1
0
1
bit 5
BRG COUNTER CLOCK
RATES
completion of the
subtract
BRG Base
bit 6
Edge #4
 2011 Microchip Technology Inc.
F
F
F
F
Clock
OSC
OSC
OSC
OSC
bit 7
/64
/16
/16
/4
“Auto-Wake-up
1
Stop bit
Edge #5
Auto Cleared
BRG ABD
001Ch
F
F
F
from
F
1Ch
00h
OSC
OSC
OSC
Clock
OSC
auto-baud
/512
/128
/128
/32
the
on