PIC16LF1906-E/MV Microchip Technology, PIC16LF1906-E/MV Datasheet - Page 183

• Manufacturer Part Number: PIC16LF1906-E/MV
• Description: 14KB Flash, 512B RAM, LCD, 11x10b ADC, EUSART, NanoWatt XLP 28 UQFN 4x4x0.5mm TU
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16LF1906-E/MV

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: LIN, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 14KB (8K x 14)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-UFQFN Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

18.4.2.3
The operation of the Synchronous Master and Slave
modes is identical
Master
• Sleep
• CREN bit is always set, therefore the receiver is
• SREN bit, which is a “don’t care” in Slave mode
A character may be received while in Sleep mode by
setting the CREN bit prior to entering Sleep. Once the
word is received, the RSR register will transfer the data
to the RCREG register. If the RCIE enable bit is set, the
interrupt generated will wake the device from Sleep
and execute the next instruction. If the GIE bit is also
set, the program will branch to the interrupt vector.
TABLE 18-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
 2011 Microchip Technology Inc.
BAUD1CON
BAUD2CON
INTCON
PIE1
PIR1
RCREG
RCSTA
SPBRGL
SPBRGH
TXSTA
Legend:
never Idle
Name
Reception”), with the following exceptions:
*
Page provides register information.
— = unimplemented locations, read as ‘0’. Shaded bits are not used for synchronous slave reception.
EUSART Synchronous Slave
Reception
TMR1GIE
TMR1GIF
ABDOVF
ABDOVF
CSRC
SPEN
Bit 7
GIE
(Section 18.4.1.6 “Synchronous
RCIDL
RCIDL
PEIE
ADIE
ADIF
Bit 6
RX9
TX9
TMR0IE
EUSART Baud Rate Generator, High Byte
EUSART Baud Rate Generator, Low Byte
SREN
TXEN
RCIE
RCIF
Bit 5
—
—
EUSART Receive Register
Preliminary
CREN
SCKP
SCKP
SYNC
INTE
Bit 4
TXIE
TXIF
ADDEN
SENDB
BRG16
BRG16
18.4.2.4
1.
2.
3.
4.
5.
6.
7.
8.
9.
IOCIE
Bit 3
—
—
Set the SYNC and SPEN bits and clear the
CSRC bit.
Set the RX/DT and TX/CK TRIS controls to ‘1’.
If using interrupts, ensure that the GIE and PEIE
bits of the INTCON register are set and set the
RCIE bit.
If 9-bit reception is desired, set the RX9 bit.
Set the CREN bit to enable reception.
The RCIF bit will be set when reception is
complete. An interrupt will be generated if the
RCIE bit was set.
If 9-bit mode is enabled, retrieve the Most
Significant bit from the RX9D bit of the RCSTA
register.
Retrieve the 8 Least Significant bits from the
receive FIFO by reading the RCREG register.
If an overrun error occurs, clear the error by
either clearing the CREN bit of the RCSTA
register or by clearing the SPEN bit which resets
the EUSART.
PIC16LF1904/6/7
TMR0IF
BRGH
FERR
Bit 2
Synchronous Slave Reception
Set-up:
—
—
—
—
OERR
TRMT
WUE
WUE
INTF
Bit 1
—
—
TMR1IE
TMR1IF
ABDEN
ABDEN
IOCIF
RX9D
TX9D
DS41569A-page 183
Bit 0
Register
on Page
160*
167*
167*
166
166
165
164
93
94
98